This file documents the GNU Assembler "as".

Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001 Free Software Foundation, Inc.

Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.1 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".

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Using as

This file is a user guide to the GNU assembler as version 2.11.90.

This document is distributed under the terms of the GNU Free Documentation License. A copy of the license is included in the section entitled "GNU Free Documentation License".

Node:Overview, Next:, Previous:Top, Up:Top

Overview

Here is a brief summary of how to invoke as. For details, see Comand-Line Options.

gcc(1), ld(1), and the Info entries for binutils and ld. 

as [ -a[cdhlns][=file] ] [ -D ]  [ --defsym sym=val ]
 [ -f ] [ --gstabs ] [ --gdwarf2 ] [ --help ] [ -I dir ]
 [ -J ] [ -K ] [ -L ]
 [ --listing--lhs-width=NUM ][ --listing-lhs-width2=NUM ]
 [ --listing-rhs-width=NUM ][ --listing-cont-lines=NUM ]
 [ --keep-locals ] [ -o objfile ] [ -R ] [ --statistics ] [ -v ]
 [ -version ] [ --version ] [ -W ] [ --warn ] [ --fatal-warnings ]
 [ -w ] [ -x ] [ -Z ] [ --target-help ]
 [ -marc[5|6|7|8] ]
 [ -EB | -EL ]
 [ -m[arm]1 | -m[arm]2 | -m[arm]250 | -m[arm]3 |
   -m[arm]6 | -m[arm]60 | -m[arm]600 | -m[arm]610 |
   -m[arm]620 | -m[arm]7[t][[d]m[i]][fe] | -m[arm]70 |
   -m[arm]700 | -m[arm]710[c] | -m[arm]7100 |
   -m[arm]7500 | -m[arm]8 | -m[arm]810 | -m[arm]9 |
   -m[arm]920 | -m[arm]920t | -m[arm]9tdmi |
   -mstrongarm | -mstrongarm110 | -mstrongarm1100 ]
 [ -m[arm]v2 | -m[arm]v2a | -m[arm]v3 | -m[arm]v3m |
   -m[arm]v4 | -m[arm]v4t | -m[arm]v5 | -[arm]v5t |
   -[arm]v5te ]
 [ -mthumb | -mall ]
 [ -mfpa10 | -mfpa11 | -mfpe-old | -mno-fpu ]
 [ -EB | -EL ]
 [ -mapcs-32 | -mapcs-26 | -mapcs-float |
   -mapcs-reentrant ]
 [ -mthumb-interwork ] [ -moabi ] [ -k ]
 [ -O ]
 [ -O | -n | -N ]
 [ -mb | -me ]
 [ -Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite
   -Av8plus | -Av8plusa | -Av9 | -Av9a ]
 [ -xarch=v8plus | -xarch=v8plusa ] [ -bump ]
 [ -32 | -64 ]
 [ -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB |
   -AKC | -AMC ]
 [ -b ] [ -no-relax ]
 [ --m32rx | --[no-]warn-explicit-parallel-conflicts |
   --W[n]p ]
 [ -l ] [ -m68000 | -m68010 | -m68020 | ... ]
 [ -jsri2bsr ] [ -sifilter ] [ -relax ]
 [ -mcpu=[210|340] ]
 [ -m68hc11 | -m68hc12 ]
 [ --force-long-branchs ] [ --short-branchs ]
 [ --strict-direct-mode ] [ --print-insn-syntax ]
 [ --print-opcodes ] [ --generate-example ]
 [ -nocpp ] [ -EL ] [ -EB ] [ -G num ] [ -mcpu=CPU ]
 [ -mips1 ] [ -mips2 ] [ -mips3 ] [ -mips4 ] [ -mips5 ]
 [ -mips32 ] [ -mips64 ]
 [ -m4650 ] [ -no-m4650 ]
 [ --trap ] [ --break ] [ -n ]
 [ --emulation=name ]
 [ -- | files ... ]
-a[cdhlmns]
Turn on listings, in any of a variety of ways:
-ac
omit false conditionals
-ad
omit debugging directives
-ah
include high-level source
-al
include assembly
-am
include macro expansions
-an
omit forms processing
-as
include symbols
=file
set the name of the listing file

You may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, -a defaults to -ahls.

-D
Ignored. This option is accepted for script compatibility with calls to other assemblers.
--defsym sym=value
Define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading 0x indicates a hexadecimal value, and a leading 0 indicates an octal value.
-f
"fast"--skip whitespace and comment preprocessing (assume source is compiler output).
--gstabs
Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.
--gdwarf2
Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note - this option is only supported by some targets, not all of them.
--help
Print a summary of the command line options and exit.
--target-help
Print a summary of all target specific options and exit.
-I dir
Add directory dir to the search list for .include directives.
-J
Don't warn about signed overflow.
-K
Issue warnings when difference tables altered for long displacements.
-L
--keep-locals
Keep (in the symbol table) local symbols. On traditional a.out systems these start with L, but different systems have different local label prefixes.
--listing-lhs-width=number
Set the maximum width, in words, of the output data column for an assembler listing to number.
--listing-lhs-width2=number
Set the maximum width, in words, of the output data column for continuation lines in an assembler listing to number.
--listing-rhs-width=number
Set the maximum width of an input source line, as displayed in a listing, to number bytes.
--listing-cont-lines=number
Set the maximum number of lines printed in a listing for a single line of input to number + 1.
-o objfile
Name the object-file output from as objfile.
-R
Fold the data section into the text section.
--statistics
Print the maximum space (in bytes) and total time (in seconds) used by assembly.
--strip-local-absolute
Remove local absolute symbols from the outgoing symbol table.
-v
-version
Print the as version.
--version
Print the as version and exit.
-W
--no-warn
Suppress warning messages.
--fatal-warnings
Treat warnings as errors.
--warn
Don't suppress warning messages or treat them as errors.
-w
Ignored.
-x
Ignored.
-Z
Generate an object file even after errors.
-- | files ...
Standard input, or source files to assemble.

The following options are available when as is configured for an ARC processor.

-marc[5|6|7|8]
This option selects the core processor variant.
-EB | -EL
Select either big-endian (-EB) or little-endian (-EL) output.

The following options are available when as is configured for the ARM processor family.

-m[arm][1|2|3|6|7|8|9][...]
Specify which ARM processor variant is the target.
-m[arm]v[2|2a|3|3m|4|4t|5|5t]
Specify which ARM architecture variant is used by the target.
-mthumb | -mall
Enable or disable Thumb only instruction decoding.
-mfpa10 | -mfpa11 | -mfpe-old | -mno-fpu
Select which Floating Point architecture is the target.
-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant | -moabi
Select which procedure calling convention is in use.
-EB | -EL
Select either big-endian (-EB) or little-endian (-EL) output.
-mthumb-interwork
Specify that the code has been generated with interworking between Thumb and ARM code in mind.
-k
Specify that PIC code has been generated.

The following options are available when as is configured for a D10V processor.

-O
Optimize output by parallelizing instructions.

The following options are available when as is configured for a D30V processor.

-O
Optimize output by parallelizing instructions.
-n
Warn when nops are generated.
-N
Warn when a nop after a 32-bit multiply instruction is generated.

The following options are available when as is configured for the Intel 80960 processor.

-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC
Specify which variant of the 960 architecture is the target.
-b
Add code to collect statistics about branches taken.
-no-relax
Do not alter compare-and-branch instructions for long displacements; error if necessary.

The following options are available when as is configured for the Mitsubishi M32R series.


--m32rx
Specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX.
--warn-explicit-parallel-conflicts or --Wp
Produce warning messages when questionable parallel constructs are encountered.
--no-warn-explicit-parallel-conflicts or --Wnp
Do not produce warning messages when questionable parallel constructs are encountered.

The following options are available when as is configured for the Motorola 68000 series.


-l
Shorten references to undefined symbols, to one word instead of two.
-m68000 | -m68008 | -m68010 | -m68020 | -m68030
| -m68040 | -m68060 | -m68302 | -m68331 | -m68332
| -m68333 | -m68340 | -mcpu32 | -m5200
Specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed at configuration time.
-m68881 | -m68882 | -mno-68881 | -mno-68882
The target machine does (or does not) have a floating-point coprocessor. The default is to assume a coprocessor for 68020, 68030, and cpu32. Although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to do emulation of the coprocessor instructions with the main processor.
-m68851 | -mno-68851
The target machine does (or does not) have a memory-management unit coprocessor. The default is to assume an MMU for 68020 and up.

For details about the PDP-11 machine dependent features options, see PDP-11-Options.

-mpic | -mno-pic
Generate position-independent (or position-dependent) code. The default is -mpic.
-mall
-mall-extensions
Enable all instruction set extensions. This is the default.
-mno-extensions
Disable all instruction set extensions.
-mextension | -mno-extension
Enable (or disable) a particular instruction set extension.
-mcpu
Enable the instruction set extensions supported by a particular CPU, and disable all other extensions.
-mmachine
Enable the instruction set extensions supported by a particular machine model, and disable all other extensions.

The following options are available when as is configured for a picoJava processor.


-mb
Generate "big endian" format output.
-ml
Generate "little endian" format output.

The following options are available when as is configured for the Motorola 68HC11 or 68HC12 series.


-m68hc11 | -m68hc12
Specify what processor is the target. The default is defined by the configuration option when building the assembler.
--force-long-branchs
Relative branches are turned into absolute ones. This concerns conditional branches, unconditional branches and branches to a sub routine.
-S | --short-branchs
Do not turn relative branchs into absolute ones when the offset is out of range.
--strict-direct-mode
Do not turn the direct addressing mode into extended addressing mode when the instruction does not support direct addressing mode.
--print-insn-syntax
Print the syntax of instruction in case of error.
--print-opcodes
print the list of instructions with syntax and then exit.
--generate-example
print an example of instruction for each possible instruction and then exit. This option is only useful for testing as.

The following options are available when as is configured for the SPARC architecture:

-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite
-Av8plus | -Av8plusa | -Av9 | -Av9a
Explicitly select a variant of the SPARC architecture.

-Av8plus and -Av8plusa select a 32 bit environment. -Av9 and -Av9a select a 64 bit environment.

-Av8plusa and -Av9a enable the SPARC V9 instruction set with UltraSPARC extensions.

-xarch=v8plus | -xarch=v8plusa
For compatibility with the Solaris v9 assembler. These options are equivalent to -Av8plus and -Av8plusa, respectively.
-bump
Warn when the assembler switches to another architecture.

The following options are available when as is configured for a MIPS processor.

-G num
This option sets the largest size of an object that can be referenced implicitly with the gp register. It is only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. The default value is 8.
-EB
Generate "big endian" format output.
-EL
Generate "little endian" format output.
-mips1
-mips2
-mips3
-mips4
-mips32
Generate code for a particular MIPS Instruction Set Architecture level. -mips1 corresponds to the R2000 and R3000 processors, -mips2 to the R6000 processor, and -mips3 to the R4000 processor. -mips5, -mips32, and -mips64 correspond to generic MIPS V, MIPS32, and MIPS64 ISA processors, respectively.
-m4650
-no-m4650
Generate code for the MIPS R4650 chip. This tells the assembler to accept the mad and madu instruction, and to not schedule nop instructions around accesses to the HI and LO registers. -no-m4650 turns off this option.
-mcpu=CPU
Generate code for a particular MIPS cpu. It is exactly equivalent to -mcpu, except that there are more value of cpu understood.
--emulation=name
This option causes as to emulate as configured for some other target, in all respects, including output format (choosing between ELF and ECOFF only), handling of pseudo-opcodes which may generate debugging information or store symbol table information, and default endianness. The available configuration names are: mipsecoff, mipself, mipslecoff, mipsbecoff, mipslelf, mipsbelf. The first two do not alter the default endianness from that of the primary target for which the assembler was configured; the others change the default to little- or big-endian as indicated by the b or l in the name. Using -EB or -EL will override the endianness selection in any case.

This option is currently supported only when the primary target as is configured for is a MIPS ELF or ECOFF target. Furthermore, the primary target or others specified with --enable-targets=... at configuration time must include support for the other format, if both are to be available. For example, the Irix 5 configuration includes support for both.

Eventually, this option will support more configurations, with more fine-grained control over the assembler's behavior, and will be supported for more processors.

-nocpp
as ignores this option. It is accepted for compatibility with the native tools.
--trap
--no-trap
--break
--no-break
Control how to deal with multiplication overflow and division by zero. --trap or --no-break (which are synonyms) take a trap exception (and only work for Instruction Set Architecture level 2 and higher); --break or --no-trap (also synonyms, and the default) take a break exception.
-n
When this option is used, as will issue a warning every time it generates a nop instruction from a macro.

The following options are available when as is configured for an MCore processor.

-jsri2bsr
-nojsri2bsr
Enable or disable the JSRI to BSR transformation. By default this is enabled. The command line option -nojsri2bsr can be used to disable it.
-sifilter
-nosifilter
Enable or disable the silicon filter behaviour. By default this is disabled. The default can be overridden by the -sifilter command line option.
-relax
Alter jump instructions for long displacements.
-mcpu=[210|340]
Select the cpu type on the target hardware. This controls which instructions can be assembled.
-EB
Assemble for a big endian target.
-EL
Assemble for a little endian target.

Node:Manual, Next:, Up:Overview

Structure of this Manual

This manual is intended to describe what you need to know to use GNU as. We cover the syntax expected in source files, including notation for symbols, constants, and expressions; the directives that as understands; and of course how to invoke as.

This manual also describes some of the machine-dependent features of various flavors of the assembler.

On the other hand, this manual is not intended as an introduction to programming in assembly language--let alone programming in general! In a similar vein, we make no attempt to introduce the machine architecture; we do not describe the instruction set, standard mnemonics, registers or addressing modes that are standard to a particular architecture. You may want to consult the manufacturer's machine architecture manual for this information.

Node:GNU Assembler, Next:, Previous:Manual, Up:Overview

The GNU Assembler

GNU as is really a family of assemblers. If you use (or have used) the GNU assembler on one architecture, you should find a fairly similar environment when you use it on another architecture. Each version has much in common with the others, including object file formats, most assembler directives (often called pseudo-ops) and assembler syntax.

as is primarily intended to assemble the output of the GNU C compiler gcc for use by the linker ld. Nevertheless, we've tried to make as assemble correctly everything that other assemblers for the same machine would assemble. Any exceptions are documented explicitly (see Machine Dependencies). This doesn't mean as always uses the same syntax as another assembler for the same architecture; for example, we know of several incompatible versions of 680x0 assembly language syntax.

Unlike older assemblers, as is designed to assemble a source program in one pass of the source file. This has a subtle impact on the .org directive (see .org).

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Object File Formats

The GNU assembler can be configured to produce several alternative object file formats. For the most part, this does not affect how you write assembly language programs; but directives for debugging symbols are typically different in different file formats. See Symbol Attributes.

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Command Line

After the program name as, the command line may contain options and file names. Options may appear in any order, and may be before, after, or between file names. The order of file names is significant.

-- (two hyphens) by itself names the standard input file explicitly, as one of the files for as to assemble.

Except for -- any command line argument that begins with a hyphen (-) is an option. Each option changes the behavior of as. No option changes the way another option works. An option is a - followed by one or more letters; the case of the letter is important. All options are optional.

Some options expect exactly one file name to follow them. The file name may either immediately follow the option's letter (compatible with older assemblers) or it may be the next command argument (GNU standard). These two command lines are equivalent: 

as -o my-object-file.o mumble.s
as -omy-object-file.o mumble.s

Node:Input Files, Next:, Previous:Command Line, Up:Overview

Input Files

We use the phrase source program, abbreviated source, to describe the program input to one run of as. The program may be in one or more files; how the source is partitioned into files doesn't change the meaning of the source.

The source program is a concatenation of the text in all the files, in the order specified.

Each time you run as it assembles exactly one source program. The source program is made up of one or more files. (The standard input is also a file.)

You give as a command line that has zero or more input file names. The input files are read (from left file name to right). A command line argument (in any position) that has no special meaning is taken to be an input file name.

If you give as no file names it attempts to read one input file from the as standard input, which is normally your terminal. You may have to type <ctl-D> to tell as there is no more program to assemble.

Use -- if you need to explicitly name the standard input file in your command line.

If the source is empty, as produces a small, empty object file.

Filenames and Line-numbers

There are two ways of locating a line in the input file (or files) and either may be used in reporting error messages. One way refers to a line number in a physical file; the other refers to a line number in a "logical" file. See Error and Warning Messages.

Physical files are those files named in the command line given to as.

Logical files are simply names declared explicitly by assembler directives; they bear no relation to physical files. Logical file names help error messages reflect the original source file, when as source is itself synthesized from other files. as understands the # directives emitted by the gcc preprocessor. See also .file.

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Output (Object) File

Every time you run as it produces an output file, which is your assembly language program translated into numbers. This file is the object file. Its default name is a.out, or b.out when as is configured for the Intel 80960. You can give it another name by using the -o option. Conventionally, object file names end with .o. The default name is used for historical reasons: older assemblers were capable of assembling self-contained programs directly into a runnable program. (For some formats, this isn't currently possible, but it can be done for the a.out format.)

The object file is meant for input to the linker ld. It contains assembled program code, information to help ld integrate the assembled program into a runnable file, and (optionally) symbolic information for the debugger.

Node:Errors, Previous:Object, Up:Overview

Error and Warning Messages

as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically. Warnings report an assumption made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly.

Warning messages have the format 

file_name:NNN:Warning Message Text

(where NNN is a line number). If a logical file name has been given (see .file) it is used for the filename, otherwise the name of the current input file is used. If a logical line number was given (see .line) then it is used to calculate the number printed, otherwise the actual line in the current source file is printed. The message text is intended to be self explanatory (in the grand Unix tradition).

Error messages have the format 

file_name:NNN:FATAL:Error Message Text
The file name and line number are derived as for warning messages. The actual message text may be rather less explanatory because many of them aren't supposed to happen.

Node:Invoking, Next:, Previous:Overview, Up:Top

Command-Line Options

This chapter describes command-line options available in all versions of the GNU assembler; see Machine Dependencies, for options specific to particular machine architectures.

If you are invoking as via the GNU C compiler (version 2), you can use the -Wa option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and the -Wa) by commas. For example: 

gcc -c -g -O -Wa,-alh,-L file.c

This passes two options to the assembler: -alh (emit a listing to standard output with with high-level and assembly source) and -L (retain local symbols in the symbol table).

Usually you do not need to use this -Wa mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. (You can call the GNU compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler.)

Node:a, Next:, Up:Invoking

Enable Listings: -a[cdhlns]

These options enable listing output from the assembler. By itself, -a requests high-level, assembly, and symbols listing. You can use other letters to select specific options for the list: -ah requests a high-level language listing, -al requests an output-program assembly listing, and -as requests a symbol table listing. High-level listings require that a compiler debugging option like -g be used, and that assembly listings (-al) be requested also.

Use the -ac option to omit false conditionals from a listing. Any lines which are not assembled because of a false .if (or .ifdef, or any other conditional), or a true .if followed by an .else, will be omitted from the listing.

Use the -ad option to omit debugging directives from the listing.

Once you have specified one of these options, you can further control listing output and its appearance using the directives .list, .nolist, .psize, .eject, .title, and .sbttl. The -an option turns off all forms processing. If you do not request listing output with one of the -a options, the listing-control directives have no effect.

The letters after -a may be combined into one option, e.g., -aln.

Note if the assembler source is coming from the standard input (eg because it is being created by gcc and the -pipe command line switch is being used) then the listing will not contain any comments or preprocessor directives. This is because the listing code buffers input source lines from stdin only after they have been preprocessed by the assembler. This reduces memory usage and makes the code more efficient.

Node:D, Next:, Previous:a, Up:Invoking

-D

This option has no effect whatsoever, but it is accepted to make it more likely that scripts written for other assemblers also work with as.

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Work Faster: -f

-f should only be used when assembling programs written by a (trusted) compiler. -f stops the assembler from doing whitespace and comment preprocessing on the input file(s) before assembling them. See Preprocessing.

Warning: if you use -f when the files actually need to be preprocessed (if they contain comments, for example), as does not work correctly.

Node:I, Next:, Previous:f, Up:Invoking

.include search path: -I path

Use this option to add a path to the list of directories as searches for files specified in .include directives (see .include). You may use -I as many times as necessary to include a variety of paths. The current working directory is always searched first; after that, as searches any -I directories in the same order as they were specified (left to right) on the command line.

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Difference Tables: -K

as sometimes alters the code emitted for directives of the form .word sym1-sym2; see .word. You can use the -K option if you want a warning issued when this is done.

Node:L, Next:, Previous:K, Up:Invoking

Include Local Labels: -L

Labels beginning with L (upper case only) are called local labels. See Symbol Names. Normally you do not see such labels when debugging, because they are intended for the use of programs (like compilers) that compose assembler programs, not for your notice. Normally both as and ld discard such labels, so you do not normally debug with them.

This option tells as to retain those L... symbols in the object file. Usually if you do this you also tell the linker ld to preserve symbols whose names begin with L.

By default, a local label is any label beginning with L, but each target is allowed to redefine the local label prefix. On the HPPA local labels begin with L$.

Node:listing, Next:, Previous:L, Up:Invoking

Configuringh listing output: --listing

The listing feature of the assembler can be enabled via the command line switch -a (see a). This feature combines the input source file(s) with a hex dump of the corresponding locations in the output object file, and displays them as a listing file. The format of this listing can be controlled by pseudo ops inside the assembler source (see List see Title see Sbttl see Psize see Eject) and also by the following switches:

--listing-lhs-width=number
Sets the maximum width, in words, of the first line of the hex byte dump. This dump appears on the left hand side of the listing output.
--listing-lhs-width2=number
Sets the maximum width, in words, of any further lines of the hex byte dump for a given inut source line. If this value is not specified, it defaults to being the same as the value specified for --listing-lhs-width. If neither switch is used the default is to one.
--listing-rhs-width=number
Sets the maximum width, in characters, of the source line that is displayed alongside the hex dump. The default value for this parameter is 100. The source line is displayed on the right hand side of the listing output.
--listing-cont-lines=number
Sets the maximum number of continuation lines of hex dump that will be displayed for a given single line of source input. The default value is 4.

Node:M, Next:, Previous:listing, Up:Invoking

Assemble in MRI Compatibility Mode: -M

The -M or --mri option selects MRI compatibility mode. This changes the syntax and pseudo-op handling of as to make it compatible with the ASM68K or the ASM960 (depending upon the configured target) assembler from Microtec Research. The exact nature of the MRI syntax will not be documented here; see the MRI manuals for more information. Note in particular that the handling of macros and macro arguments is somewhat different. The purpose of this option is to permit assembling existing MRI assembler code using as.

The MRI compatibility is not complete. Certain operations of the MRI assembler depend upon its object file format, and can not be supported using other object file formats. Supporting these would require enhancing each object file format individually. These are:

There are some other features of the MRI assembler which are not supported by as, typically either because they are difficult or because they seem of little consequence. Some of these may be supported in future releases.

Node:MD, Next:, Previous:M, Up:Invoking

Dependency tracking: --MD

as can generate a dependency file for the file it creates. This file consists of a single rule suitable for make describing the dependencies of the main source file.

The rule is written to the file named in its argument.

This feature is used in the automatic updating of makefiles.

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Name the Object File: -o

There is always one object file output when you run as. By default it has the name a.out (or b.out, for Intel 960 targets only). You use this option (which takes exactly one filename) to give the object file a different name.

Whatever the object file is called, as overwrites any existing file of the same name.

Node:R, Next:, Previous:o, Up:Invoking

Join Data and Text Sections: -R

-R tells as to write the object file as if all data-section data lives in the text section. This is only done at the very last moment: your binary data are the same, but data section parts are relocated differently. The data section part of your object file is zero bytes long because all its bytes are appended to the text section. (See Sections and Relocation.)

When you specify -R it would be possible to generate shorter address displacements (because we do not have to cross between text and data section). We refrain from doing this simply for compatibility with older versions of as. In future, -R may work this way.

When as is configured for COFF output, this option is only useful if you use sections named .text and .data.

-R is not supported for any of the HPPA targets. Using -R generates a warning from as.

Node:statistics, Next:, Previous:R, Up:Invoking

Display Assembly Statistics: --statistics

Use --statistics to display two statistics about the resources used by as: the maximum amount of space allocated during the assembly (in bytes), and the total execution time taken for the assembly (in CPU seconds).

Node:traditional-format, Next:, Previous:statistics, Up:Invoking

Compatible output: --traditional-format

For some targets, the output of as is different in some ways from the output of some existing assembler. This switch requests as to use the traditional format instead.

For example, it disables the exception frame optimizations which as normally does by default on gcc output.

Node:v, Next:, Previous:traditional-format, Up:Invoking

Announce Version: -v

You can find out what version of as is running by including the option -v (which you can also spell as -version) on the command line.

Node:W, Next:, Previous:v, Up:Invoking

Control Warnings: -W, --warn, --no-warn, --fatal-warnings

as should never give a warning or error message when assembling compiler output. But programs written by people often cause as to give a warning that a particular assumption was made. All such warnings are directed to the standard error file.

If you use the -W and --no-warn options, no warnings are issued. This only affects the warning messages: it does not change any particular of how as assembles your file. Errors, which stop the assembly, are still reported.

If you use the --fatal-warnings option, as considers files that generate warnings to be in error.

You can switch these options off again by specifying --warn, which causes warnings to be output as usual.

Node:Z, Previous:W, Up:Invoking

Generate Object File in Spite of Errors: -Z

After an error message, as normally produces no output. If for some reason you are interested in object file output even after as gives an error message on your program, use the -Z option. If there are any errors, as continues anyways, and writes an object file after a final warning message of the form n errors, m warnings, generating bad object file.

Node:Syntax, Next:, Previous:Invoking, Up:Top

Syntax

This chapter describes the machine-independent syntax allowed in a source file. as syntax is similar to what many other assemblers use; it is inspired by the BSD 4.2 assembler, except that as does not assemble Vax bit-fields.

Node:Preprocessing, Next:, Up:Syntax

Preprocessing

The as internal preprocessor:

It does not do macro processing, include file handling, or anything else you may get from your C compiler's preprocessor. You can do include file processing with the .include directive (see .include). You can use the GNU C compiler driver to get other "CPP" style preprocessing, by giving the input file a .S suffix. See Overall Options.

Excess whitespace, comments, and character constants cannot be used in the portions of the input text that are not preprocessed.

If the first line of an input file is #NO_APP or if you use the -f option, whitespace and comments are not removed from the input file. Within an input file, you can ask for whitespace and comment removal in specific portions of the by putting a line that says #APP before the text that may contain whitespace or comments, and putting a line that says #NO_APP after this text. This feature is mainly intend to support asm statements in compilers whose output is otherwise free of comments and whitespace.

Node:Whitespace, Next:, Previous:Preprocessing, Up:Syntax

Whitespace

Whitespace is one or more blanks or tabs, in any order. Whitespace is used to separate symbols, and to make programs neater for people to read. Unless within character constants (see Character Constants), any whitespace means the same as exactly one space.

Node:Comments, Next:, Previous:Whitespace, Up:Syntax

Comments

There are two ways of rendering comments to as. In both cases the comment is equivalent to one space.

Anything from /* through the next */ is a comment. This means you may not nest these comments. 

/*
  The only way to include a newline ('\n') in a comment
  is to use this sort of comment.
*/

/* This sort of comment does not nest. */

Anything from the line comment character to the next newline is considered a comment and is ignored. The line comment character is ; for the AMD 29K family; ; on the ARC; @ on the ARM; ; for the H8/300 family; ! for the H8/500 family; ; for the HPPA; # on the i386 and x86-64; # on the i960; ; for the PDP-11; ; for picoJava; ! for the Hitachi SH; ! on the SPARC; # on the m32r; | on the 680x0; # on the 68HC11 and 68HC12; ; on the M880x0; # on the Vax; ! for the Z8000; # on the V850; see Machine Dependencies.

On some machines there are two different line comment characters. One character only begins a comment if it is the first non-whitespace character on a line, while the other always begins a comment.

The V850 assembler also supports a double dash as starting a comment that extends to the end of the line.

--;

To be compatible with past assemblers, lines that begin with # have a special interpretation. Following the # should be an absolute expression (see Expressions): the logical line number of the next line. Then a string (see Strings) is allowed: if present it is a new logical file name. The rest of the line, if any, should be whitespace.

If the first non-whitespace characters on the line are not numeric, the line is ignored. (Just like a comment.) 

                          # This is an ordinary comment.
# 42-6 "new_file_name"    # New logical file name
                          # This is logical line # 36.
This feature is deprecated, and may disappear from future versions of as.

Node:Symbol Intro, Next:, Previous:Comments, Up:Syntax

Symbols

A symbol is one or more characters chosen from the set of all letters (both upper and lower case), digits and the three characters _.$. On most machines, you can also use $ in symbol names; exceptions are noted in Machine Dependencies. No symbol may begin with a digit. Case is significant. There is no length limit: all characters are significant. Symbols are delimited by characters not in that set, or by the beginning of a file (since the source program must end with a newline, the end of a file is not a possible symbol delimiter). See Symbols.

Node:Statements, Next:, Previous:Symbol Intro, Up:Syntax

Statements

A statement ends at a newline character (\n) or line separator character. (The line separator is usually ;, unless this conflicts with the comment character; see Machine Dependencies.) The newline or separator character is considered part of the preceding statement. Newlines and separators within character constants are an exception: they do not end statements.

It is an error to end any statement with end-of-file: the last character of any input file should be a newline.

An empty statement is allowed, and may include whitespace. It is ignored.

A statement begins with zero or more labels, optionally followed by a key symbol which determines what kind of statement it is. The key symbol determines the syntax of the rest of the statement. If the symbol begins with a dot . then the statement is an assembler directive: typically valid for any computer. If the symbol begins with a letter the statement is an assembly language instruction: it assembles into a machine language instruction. Different versions of as for different computers recognize different instructions. In fact, the same symbol may represent a different instruction in a different computer's assembly language.

A label is a symbol immediately followed by a colon (:). Whitespace before a label or after a colon is permitted, but you may not have whitespace between a label's symbol and its colon. See Labels.

For HPPA targets, labels need not be immediately followed by a colon, but the definition of a label must begin in column zero. This also implies that only one label may be defined on each line. 

label:     .directive    followed by something
another_label:           # This is an empty statement.
           instruction   operand_1, operand_2, ...

Node:Constants, Previous:Statements, Up:Syntax

Constants

A constant is a number, written so that its value is known by inspection, without knowing any context. Like this: 

.byte  74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value.
.ascii "Ring the bell\7"                  # A string constant.
.octa  0x123456789abcdef0123456789ABCDEF0 # A bignum.
.float 0f-314159265358979323846264338327\
95028841971.693993751E-40                 # - pi, a flonum.

Node:Characters, Next:, Up:Constants

Character Constants

There are two kinds of character constants. A character stands for one character in one byte and its value may be used in numeric expressions. String constants (properly called string literals) are potentially many bytes and their values may not be used in arithmetic expressions.

Node:Strings, Next:, Up:Characters

Strings

A string is written between double-quotes. It may contain double-quotes or null characters. The way to get special characters into a string is to escape these characters: precede them with a backslash \ character. For example \\ represents one backslash: the first \ is an escape which tells as to interpret the second character literally as a backslash (which prevents as from recognizing the second \ as an escape character). The complete list of escapes follows.

\b
Mnemonic for backspace; for ASCII this is octal code 010.
\f
Mnemonic for FormFeed; for ASCII this is octal code 014.
\n
Mnemonic for newline; for ASCII this is octal code 012.
\r
Mnemonic for carriage-Return; for ASCII this is octal code 015.
\t
Mnemonic for horizontal Tab; for ASCII this is octal code 011.
\ digit digit digit
An octal character code. The numeric code is 3 octal digits. For compatibility with other Unix systems, 8 and 9 are accepted as digits: for example, \008 has the value 010, and \009 the value 011.
\x hex-digits...
A hex character code. All trailing hex digits are combined. Either upper or lower case x works.
\\
Represents one \ character.
\"
Represents one " character. Needed in strings to represent this character, because an unescaped " would end the string.
\ anything-else
Any other character when escaped by \ gives a warning, but assembles as if the \ was not present. The idea is that if you used an escape sequence you clearly didn't want the literal interpretation of the following character. However as has no other interpretation, so as knows it is giving you the wrong code and warns you of the fact.

Which characters are escapable, and what those escapes represent, varies widely among assemblers. The current set is what we think the BSD 4.2 assembler recognizes, and is a subset of what most C compilers recognize. If you are in doubt, do not use an escape sequence.

Node:Chars, Previous:Strings, Up:Characters

Characters

A single character may be written as a single quote immediately followed by that character. The same escapes apply to characters as to strings. So if you want to write the character backslash, you must write '\\ where the first \ escapes the second \. As you can see, the quote is an acute accent, not a grave accent. A newline immediately following an acute accent is taken as a literal character and does not count as the end of a statement. The value of a character constant in a numeric expression is the machine's byte-wide code for that character. as assumes your character code is ASCII: 'A means 65, 'B means 66, and so on.

Node:Numbers, Previous:Characters, Up:Constants

Number Constants

as distinguishes three kinds of numbers according to how they are stored in the target machine. Integers are numbers that would fit into an int in the C language. Bignums are integers, but they are stored in more than 32 bits. Flonums are floating point numbers, described below.

Node:Integers, Next:, Up:Numbers

Integers

A binary integer is 0b or 0B followed by zero or more of the binary digits 01.

An octal integer is 0 followed by zero or more of the octal digits (01234567).

A decimal integer starts with a non-zero digit followed by zero or more digits (0123456789).

A hexadecimal integer is 0x or 0X followed by one or more hexadecimal digits chosen from 0123456789abcdefABCDEF.

Integers have the usual values. To denote a negative integer, use the prefix operator - discussed under expressions (see Prefix Operators).

Node:Bignums, Next:, Previous:Integers, Up:Numbers

Bignums

A bignum has the same syntax and semantics as an integer except that the number (or its negative) takes more than 32 bits to represent in binary. The distinction is made because in some places integers are permitted while bignums are not.

Node:Flonums, Previous:Bignums, Up:Numbers

Flonums

A flonum represents a floating point number. The translation is indirect: a decimal floating point number from the text is converted by as to a generic binary floating point number of more than sufficient precision. This generic floating point number is converted to a particular computer's floating point format (or formats) by a portion of as specialized to that computer.

A flonum is written by writing (in order)

At least one of the integer part or the fractional part must be present. The floating point number has the usual base-10 value.

as does all processing using integers. Flonums are computed independently of any floating point hardware in the computer running as.

Node:Sections, Next:, Previous:Syntax, Up:Top

Sections and Relocation

Node:Secs Background, Next:, Up:Sections

Background

Roughly, a section is a range of addresses, with no gaps; all data "in" those addresses is treated the same for some particular purpose. For example there may be a "read only" section.

The linker ld reads many object files (partial programs) and combines their contents to form a runnable program. When as emits an object file, the partial program is assumed to start at address 0. ld assigns the final addresses for the partial program, so that different partial programs do not overlap. This is actually an oversimplification, but it suffices to explain how as uses sections.

ld moves blocks of bytes of your program to their run-time addresses. These blocks slide to their run-time addresses as rigid units; their length does not change and neither does the order of bytes within them. Such a rigid unit is called a section. Assigning run-time addresses to sections is called relocation. It includes the task of adjusting mentions of object-file addresses so they refer to the proper run-time addresses. For the H8/300 and H8/500, and for the Hitachi SH, as pads sections if needed to ensure they end on a word (sixteen bit) boundary.

An object file written by as has at least three sections, any of which may be empty. These are named text, data and bss sections.

When it generates COFF output, as can also generate whatever other named sections you specify using the .section directive (see .section). If you do not use any directives that place output in the .text or .data sections, these sections still exist, but are empty.

When as generates SOM or ELF output for the HPPA, as can also generate whatever other named sections you specify using the .space and .subspace directives. See HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001) for details on the .space and .subspace assembler directives.

Additionally, as uses different names for the standard text, data, and bss sections when generating SOM output. Program text is placed into the $CODE$ section, data into $DATA$, and BSS into $BSS$.

Within the object file, the text section starts at address 0, the data section follows, and the bss section follows the data section.

When generating either SOM or ELF output files on the HPPA, the text section starts at address 0, the data section at address 0x4000000, and the bss section follows the data section.

To let ld know which data changes when the sections are relocated, and how to change that data, as also writes to the object file details of the relocation needed. To perform relocation ld must know, each time an address in the object file is mentioned:

In fact, every address as ever uses is expressed as 

(section) + (offset into section)

Further, most expressions as computes have this section-relative nature. (For some object formats, such as SOM for the HPPA, some expressions are symbol-relative instead.)

In this manual we use the notation {secname N} to mean "offset N into section secname."

Apart from text, data and bss sections you need to know about the absolute section. When ld mixes partial programs, addresses in the absolute section remain unchanged. For example, address {absolute 0} is "relocated" to run-time address 0 by ld. Although the linker never arranges two partial programs' data sections with overlapping addresses after linking, by definition their absolute sections must overlap. Address {absolute 239} in one part of a program is always the same address when the program is running as address {absolute 239} in any other part of the program.

The idea of sections is extended to the undefined section. Any address whose section is unknown at assembly time is by definition rendered {undefined U}--where U is filled in later. Since numbers are always defined, the only way to generate an undefined address is to mention an undefined symbol. A reference to a named common block would be such a symbol: its value is unknown at assembly time so it has section undefined.

By analogy the word section is used to describe groups of sections in the linked program. ld puts all partial programs' text sections in contiguous addresses in the linked program. It is customary to refer to the text section of a program, meaning all the addresses of all partial programs' text sections. Likewise for data and bss sections.

Some sections are manipulated by ld; others are invented for use of as and have no meaning except during assembly.

Node:Ld Sections, Next:, Previous:Secs Background, Up:Sections

Linker Sections

ld deals with just four kinds of sections, summarized below.


named sections
text section
data section
These sections hold your program. as and ld treat them as separate but equal sections. Anything you can say of one section is true another. When the program is running, however, it is customary for the text section to be unalterable. The text section is often shared among processes: it contains instructions, constants and the like. The data section of a running program is usually alterable: for example, C variables would be stored in the data section.
bss section
This section contains zeroed bytes when your program begins running. It is used to hold uninitialized variables or common storage. The length of each partial program's bss section is important, but because it starts out containing zeroed bytes there is no need to store explicit zero bytes in the object file. The bss section was invented to eliminate those explicit zeros from object files.
absolute section
Address 0 of this section is always "relocated" to runtime address 0. This is useful if you want to refer to an address that ld must not change when relocating. In this sense we speak of absolute addresses being "unrelocatable": they do not change during relocation.
undefined section
This "section" is a catch-all for address references to objects not in the preceding sections.

An idealized example of three relocatable sections follows. The example uses the traditional section names .text and .data. Memory addresses are on the horizontal axis. 

                      +-----+----+--+
partial program # 1:  |ttttt|dddd|00|
                      +-----+----+--+

                      text   data bss
                      seg.   seg. seg.

                      +---+---+---+
partial program # 2:  |TTT|DDD|000|
                      +---+---+---+

                      +--+---+-----+--+----+---+-----+~~
linked program:       |  |TTT|ttttt|  |dddd|DDD|00000|
                      +--+---+-----+--+----+---+-----+~~

    addresses:        0 ...

Node:As Sections, Next:, Previous:Ld Sections, Up:Sections

Assembler Internal Sections

These sections are meant only for the internal use of as. They have no meaning at run-time. You do not really need to know about these sections for most purposes; but they can be mentioned in as warning messages, so it might be helpful to have an idea of their meanings to as. These sections are used to permit the value of every expression in your assembly language program to be a section-relative address.

ASSEMBLER-INTERNAL-LOGIC-ERROR!
An internal assembler logic error has been found. This means there is a bug in the assembler.
expr section
The assembler stores complex expression internally as combinations of symbols. When it needs to represent an expression as a symbol, it puts it in the expr section.

Node:Sub-Sections, Next:, Previous:As Sections, Up:Sections

Sub-Sections

Assembled bytes conventionally fall into two sections: text and data. You may have separate groups of data in named sections that you want to end up near to each other in the object file, even though they are not contiguous in the assembler source. as allows you to use subsections for this purpose. Within each section, there can be numbered subsections with values from 0 to 8192. Objects assembled into the same subsection go into the object file together with other objects in the same subsection. For example, a compiler might want to store constants in the text section, but might not want to have them interspersed with the program being assembled. In this case, the compiler could issue a .text 0 before each section of code being output, and a .text 1 before each group of constants being output.

Subsections are optional. If you do not use subsections, everything goes in subsection number zero.

Each subsection is zero-padded up to a multiple of four bytes. (Subsections may be padded a different amount on different flavors of as.)

Subsections appear in your object file in numeric order, lowest numbered to highest. (All this to be compatible with other people's assemblers.) The object file contains no representation of subsections; ld and other programs that manipulate object files see no trace of them. They just see all your text subsections as a text section, and all your data subsections as a data section.

To specify which subsection you want subsequent statements assembled into, use a numeric argument to specify it, in a .text expression or a .data expression statement. When generating COFF output, you can also use an extra subsection argument with arbitrary named sections: .section name, expression. Expression should be an absolute expression. (See Expressions.) If you just say .text then .text 0 is assumed. Likewise .data means .data 0. Assembly begins in text 0. For instance: 

.text 0     # The default subsection is text 0 anyway.
.ascii "This lives in the first text subsection. *"
.text 1
.ascii "But this lives in the second text subsection."
.data 0
.ascii "This lives in the data section,"
.ascii "in the first data subsection."
.text 0
.ascii "This lives in the first text section,"
.ascii "immediately following the asterisk (*)."

Each section has a location counter incremented by one for every byte assembled into that section. Because subsections are merely a convenience restricted to as there is no concept of a subsection location counter. There is no way to directly manipulate a location counter--but the .align directive changes it, and any label definition captures its current value. The location counter of the section where statements are being assembled is said to be the active location counter.

Node:bss, Previous:Sub-Sections, Up:Sections

bss Section

The bss section is used for local common variable storage. You may allocate address space in the bss section, but you may not dictate data to load into it before your program executes. When your program starts running, all the contents of the bss section are zeroed bytes.

The .lcomm pseudo-op defines a symbol in the bss section; see .lcomm.

The .comm pseudo-op may be used to declare a common symbol, which is another form of uninitialized symbol; see See .comm.

When assembling for a target which supports multiple sections, such as ELF or COFF, you may switch into the .bss section and define symbols as usual; see .section. You may only assemble zero values into the section. Typically the section will only contain symbol definitions and .skip directives (see .skip).

Node:Symbols, Next:, Previous:Sections, Up:Top

Symbols

Symbols are a central concept: the programmer uses symbols to name things, the linker uses symbols to link, and the debugger uses symbols to debug.

Warning: as does not place symbols in the object file in the same order they were declared. This may break some debuggers.

Node:Labels, Next:, Up:Symbols

Labels

A label is written as a symbol immediately followed by a colon :. The symbol then represents the current value of the active location counter, and is, for example, a suitable instruction operand. You are warned if you use the same symbol to represent two different locations: the first definition overrides any other definitions.

On the HPPA, the usual form for a label need not be immediately followed by a colon, but instead must start in column zero. Only one label may be defined on a single line. To work around this, the HPPA version of as also provides a special directive .label for defining labels more flexibly.

Node:Setting Symbols, Next:, Previous:Labels, Up:Symbols

Giving Symbols Other Values

A symbol can be given an arbitrary value by writing a symbol, followed by an equals sign =, followed by an expression (see Expressions). This is equivalent to using the .set directive. See .set.

Node:Symbol Names, Next:, Previous:Setting Symbols, Up:Symbols

Symbol Names

Symbol names begin with a letter or with one of ._. On most machines, you can also use $ in symbol names; exceptions are noted in Machine Dependencies. That character may be followed by any string of digits, letters, dollar signs (unless otherwise noted in Machine Dependencies), and underscores. For the AMD 29K family, ? is also allowed in the body of a symbol name, though not at its beginning.

Case of letters is significant: foo is a different symbol name than Foo.

Each symbol has exactly one name. Each name in an assembly language program refers to exactly one symbol. You may use that symbol name any number of times in a program.

Local Symbol Names

Local symbols help compilers and programmers use names temporarily. There are ten local symbol names, which are re-used throughout the program. You may refer to them using the names 0 1 ... 9. To define a local symbol, write a label of the form N: (where N represents any digit). To refer to the most recent previous definition of that symbol write Nb, using the same digit as when you defined the label. To refer to the next definition of a local label, write Nf--where N gives you a choice of 10 forward references. The b stands for "backwards" and the f stands for "forwards".

Local symbols are not emitted by the current GNU C compiler.

There is no restriction on how you can use these labels, but remember that at any point in the assembly you can refer to at most 10 prior local labels and to at most 10 forward local labels.

Local symbol names are only a notation device. They are immediately transformed into more conventional symbol names before the assembler uses them. The symbol names stored in the symbol table, appearing in error messages and optionally emitted to the object file have these parts:

L
All local labels begin with L. Normally both as and ld forget symbols that start with L. These labels are used for symbols you are never intended to see. If you use the -L option then as retains these symbols in the object file. If you also instruct ld to retain these symbols, you may use them in debugging.
digit
If the label is written 0: then the digit is 0. If the label is written 1: then the digit is 1. And so on up through 9:.
C-A
This unusual character is included so you do not accidentally invent a symbol of the same name. The character has ASCII value \001.
ordinal number
This is a serial number to keep the labels distinct. The first 0: gets the number 1; The 15th 0: gets the number 15; etc.. Likewise for the other labels 1: through 9:.

For instance, the first 1: is named L1C-A1, the 44th 3: is named L3C-A44.

Node:Dot, Next:, Previous:Symbol Names, Up:Symbols

The Special Dot Symbol

The special symbol . refers to the current address that as is assembling into. Thus, the expression melvin: .long . defines melvin to contain its own address. Assigning a value to . is treated the same as a .org directive. Thus, the expression .=.+4 is the same as saying .space 4.

Node:Symbol Attributes, Previous:Dot, Up:Symbols

Symbol Attributes

Every symbol has, as well as its name, the attributes "Value" and "Type". Depending on output format, symbols can also have auxiliary attributes.

If you use a symbol without defining it, as assumes zero for all these attributes, and probably won't warn you. This makes the symbol an externally defined symbol, which is generally what you would want.

Node:Symbol Value, Next:, Up:Symbol Attributes

Value

The value of a symbol is (usually) 32 bits. For a symbol which labels a location in the text, data, bss or absolute sections the value is the number of addresses from the start of that section to the label. Naturally for text, data and bss sections the value of a symbol changes as ld changes section base addresses during linking. Absolute symbols' values do not change during linking: that is why they are called absolute.

The value of an undefined symbol is treated in a special way. If it is 0 then the symbol is not defined in this assembler source file, and ld tries to determine its value from other files linked into the same program. You make this kind of symbol simply by mentioning a symbol name without defining it. A non-zero value represents a .comm common declaration. The value is how much common storage to reserve, in bytes (addresses). The symbol refers to the first address of the allocated storage.

Node:Symbol Type, Next:, Previous:Symbol Value, Up:Symbol Attributes

Type

The type attribute of a symbol contains relocation (section) information, any flag settings indicating that a symbol is external, and (optionally), other information for linkers and debuggers. The exact format depends on the object-code output format in use.

Node:a.out Symbols, Next:, Previous:Symbol Type, Up:Symbol Attributes

Symbol Attributes: a.out

Node:Symbol Desc, Next:, Up:a.out Symbols

Descriptor

This is an arbitrary 16-bit value. You may establish a symbol's descriptor value by using a .desc statement (see .desc). A descriptor value means nothing to as.

Node:Symbol Other, Previous:Symbol Desc, Up:a.out Symbols

Other

This is an arbitrary 8-bit value. It means nothing to as.

Node:COFF Symbols, Next:, Previous:a.out Symbols, Up:Symbol Attributes

Symbol Attributes for COFF

The COFF format supports a multitude of auxiliary symbol attributes; like the primary symbol attributes, they are set between .def and .endef directives.

Primary Attributes

The symbol name is set with .def; the value and type, respectively, with .val and .type.

Auxiliary Attributes

The as directives .dim, .line, .scl, .size, and .tag can generate auxiliary symbol table information for COFF.

Node:SOM Symbols, Previous:COFF Symbols, Up:Symbol Attributes

Symbol Attributes for SOM

The SOM format for the HPPA supports a multitude of symbol attributes set with the .EXPORT and .IMPORT directives.

The attributes are described in HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001) under the IMPORT and EXPORT assembler directive documentation.

Node:Expressions, Next:, Previous:Symbols, Up:Top

Expressions

An expression specifies an address or numeric value. Whitespace may precede and/or follow an expression.

The result of an expression must be an absolute number, or else an offset into a particular section. If an expression is not absolute, and there is not enough information when as sees the expression to know its section, a second pass over the source program might be necessary to interpret the expression--but the second pass is currently not implemented. as aborts with an error message in this situation.

Node:Empty Exprs, Next:, Up:Expressions

Empty Expressions

An empty expression has no value: it is just whitespace or null. Wherever an absolute expression is required, you may omit the expression, and as assumes a value of (absolute) 0. This is compatible with other assemblers.

Node:Integer Exprs, Previous:Empty Exprs, Up:Expressions

Integer Expressions

An integer expression is one or more arguments delimited by operators.

Node:Arguments, Next:, Up:Integer Exprs

Arguments

Arguments are symbols, numbers or subexpressions. In other contexts arguments are sometimes called "arithmetic operands". In this manual, to avoid confusing them with the "instruction operands" of the machine language, we use the term "argument" to refer to parts of expressions only, reserving the word "operand" to refer only to machine instruction operands.

Symbols are evaluated to yield {section NNN} where section is one of text, data, bss, absolute, or undefined. NNN is a signed, 2's complement 32 bit integer.

Numbers are usually integers.

A number can be a flonum or bignum. In this case, you are warned that only the low order 32 bits are used, and as pretends these 32 bits are an integer. You may write integer-manipulating instructions that act on exotic constants, compatible with other assemblers.

Subexpressions are a left parenthesis ( followed by an integer expression, followed by a right parenthesis ); or a prefix operator followed by an argument.

Node:Operators, Next:, Previous:Arguments, Up:Integer Exprs

Operators

Operators are arithmetic functions, like + or %. Prefix operators are followed by an argument. Infix operators appear between their arguments. Operators may be preceded and/or followed by whitespace.

Node:Prefix Ops, Next:, Previous:Operators, Up:Integer Exprs

Prefix Operator

as has the following prefix operators. They each take one argument, which must be absolute.

-
Negation. Two's complement negation.
~
Complementation. Bitwise not.

Node:Infix Ops, Previous:Prefix Ops, Up:Integer Exprs

Infix Operators

Infix operators take two arguments, one on either side. Operators have precedence, but operations with equal precedence are performed left to right. Apart from + or -, both arguments must be absolute, and the result is absolute.

  1. Highest Precedence
    *
    Multiplication.
    /
    Division. Truncation is the same as the C operator /
    %
    Remainder.
    <
    <<
    Shift Left. Same as the C operator <<.
    >
    >>
    Shift Right. Same as the C operator >>.
  2. Intermediate precedence
    |
    Bitwise Inclusive Or.
    &
    Bitwise And.
    ^
    Bitwise Exclusive Or.
    !
    Bitwise Or Not.
  3. Low Precedence
    +
    Addition. If either argument is absolute, the result has the section of the other argument. You may not add together arguments from different sections.
    -
    Subtraction. If the right argument is absolute, the result has the section of the left argument. If both arguments are in the same section, the result is absolute. You may not subtract arguments from different sections.
    ==
    Is Equal To
    <>
    Is Not Equal To
    <
    Is Less Than
    >
    Is Greater Than
    >=
    Is Greater Than Or Equal To
    <=
    Is Less Than Or Equal To

    The comparison operators can be used as infix operators. A true results has a value of -1 whereas a false result has a value of 0. Note, these operators perform signed comparisons.

  4. Lowest Precedence
    &&
    Logical And.
    ||
    Logical Or.

    These two logical operations can be used to combine the results of sub expressions. Note, unlike the comparison operators a true result returns a value of 1 but a false results does still return 0. Also note that the logical or operator has a slightly lower precedence than logical and.

In short, it's only meaningful to add or subtract the offsets in an address; you can only have a defined section in one of the two arguments.

Node:Pseudo Ops, Next:, Previous:Expressions, Up:Top

Assembler Directives

All assembler directives have names that begin with a period (.). The rest of the name is letters, usually in lower case.

This chapter discusses directives that are available regardless of the target machine configuration for the GNU assembler. Some machine configurations provide additional directives. See Machine Dependencies.

Node:Abort, Next:, Up:Pseudo Ops

.abort

This directive stops the assembly immediately. It is for compatibility with other assemblers. The original idea was that the assembly language source would be piped into the assembler. If the sender of the source quit, it could use this directive tells as to quit also. One day .abort will not be supported.

Node:ABORT, Next:, Previous:Abort, Up:Pseudo Ops

.ABORT

When producing COFF output, as accepts this directive as a synonym for .abort.

When producing b.out output, as accepts this directive, but ignores it.

Node:Align, Next:, Previous:ABORT, Up:Pseudo Ops

.align abs-expr, abs-expr, abs-expr

Pad the location counter (in the current subsection) to a particular storage boundary. The first expression (which must be absolute) is the alignment required, as described below.

The second expression (also absolute) gives the fill value to be stored in the padding bytes. It (and the comma) may be omitted. If it is omitted, the padding bytes are normally zero. However, on some systems, if the section is marked as containing code and the fill value is omitted, the space is filled with no-op instructions.

The third expression is also absolute, and is also optional. If it is present, it is the maximum number of bytes that should be skipped by this alignment directive. If doing the alignment would require skipping more bytes than the specified maximum, then the alignment is not done at all. You can omit the fill value (the second argument) entirely by simply using two commas after the required alignment; this can be useful if you want the alignment to be filled with no-op instructions when appropriate.

The way the required alignment is specified varies from system to system. For the a29k, hppa, m68k, m88k, w65, sparc, and Hitachi SH, and i386 using ELF format, the first expression is the alignment request in bytes. For example .align 8 advances the location counter until it is a multiple of 8. If the location counter is already a multiple of 8, no change is needed.

For other systems, including the i386 using a.out format, and the arm and strongarm, it is the number of low-order zero bits the location counter must have after advancement. For example .align 3 advances the location counter until it a multiple of 8. If the location counter is already a multiple of 8, no change is needed.

This inconsistency is due to the different behaviors of the various native assemblers for these systems which GAS must emulate. GAS also provides .balign and .p2align directives, described later, which have a consistent behavior across all architectures (but are specific to GAS).

Node:Ascii, Next:, Previous:Align, Up:Pseudo Ops

.ascii "string"...

.ascii expects zero or more string literals (see Strings) separated by commas. It assembles each string (with no automatic trailing zero byte) into consecutive addresses.

Node:Asciz, Next:, Previous:Ascii, Up:Pseudo Ops

.asciz "string"...

.asciz is just like .ascii, but each string is followed by a zero byte. The "z" in .asciz stands for "zero".

Node:Balign, Next:, Previous:Asciz, Up:Pseudo Ops

.balign[wl] abs-expr, abs-expr, abs-expr

Pad the location counter (in the current subsection) to a particular storage boundary. The first expression (which must be absolute) is the alignment request in bytes. For example .balign 8 advances the location counter until it is a multiple of 8. If the location counter is already a multiple of 8, no change is needed.

The second expression (also absolute) gives the fill value to be stored in the padding bytes. It (and the comma) may be omitted. If it is omitted, the padding bytes are normally zero. However, on some systems, if the section is marked as containing code and the fill value is omitted, the space is filled with no-op instructions.

The third expression is also absolute, and is also optional. If it is present, it is the maximum number of bytes that should be skipped by this alignment directive. If doing the alignment would require skipping more bytes than the specified maximum, then the alignment is not done at all. You can omit the fill value (the second argument) entirely by simply using two commas after the required alignment; this can be useful if you want the alignment to be filled with no-op instructions when appropriate.

The .balignw and .balignl directives are variants of the .balign directive. The .balignw directive treats the fill pattern as a two byte word value. The .balignl directives treats the fill pattern as a four byte longword value. For example, .balignw 4,0x368d will align to a multiple of 4. If it skips two bytes, they will be filled in with the value 0x368d (the exact placement of the bytes depends upon the endianness of the processor). If it skips 1 or 3 bytes, the fill value is undefined.

Node:Byte, Next:, Previous:Balign, Up:Pseudo Ops

.byte expressions

.byte expects zero or more expressions, separated by commas. Each expression is assembled into the next byte.

Node:Comm, Next:, Previous:Byte, Up:Pseudo Ops

.comm symbol , length

.comm declares a common symbol named symbol. When linking, a common symbol in one object file may be merged with a defined or common symbol of the same name in another object file. If ld does not see a definition for the symbol-just one or more common symbols-then it will allocate length bytes of uninitialized memory. length must be an absolute expression. If ld sees multiple common symbols with the same name, and they do not all have the same size, it will allocate space using the largest size.

When using ELF, the .comm directive takes an optional third argument. This is the desired alignment of the symbol, specified as a byte boundary (for example, an alignment of 16 means that the least significant 4 bits of the address should be zero). The alignment must be an absolute expression, and it must be a power of two. If ld allocates uninitialized memory for the common symbol, it will use the alignment when placing the symbol. If no alignment is specified, as will set the alignment to the largest power of two less than or equal to the size of the symbol, up to a maximum of 16.

The syntax for .comm differs slightly on the HPPA. The syntax is symbol .comm, length; symbol is optional.

Node:Data, Next:, Previous:Comm, Up:Pseudo Ops

.data subsection

.data tells as to assemble the following statements onto the end of the data subsection numbered subsection (which is an absolute expression). If subsection is omitted, it defaults to zero.

Node:Def, Next:, Previous:Data, Up:Pseudo Ops

.def name

Begin defining debugging information for a symbol name; the definition extends until the .endef directive is encountered.

This directive is only observed when as is configured for COFF format output; when producing b.out, .def is recognized, but ignored.

Node:Desc, Next:, Previous:Def, Up:Pseudo Ops

.desc symbol, abs-expression

This directive sets the descriptor of the symbol (see Symbol Attributes) to the low 16 bits of an absolute expression.

The .desc directive is not available when as is configured for COFF output; it is only for a.out or b.out object format. For the sake of compatibility, as accepts it, but produces no output, when configured for COFF.

Node:Dim, Next:, Previous:Desc, Up:Pseudo Ops

.dim

This directive is generated by compilers to include auxiliary debugging information in the symbol table. It is only permitted inside .def/.endef pairs.

.dim is only meaningful when generating COFF format output; when as is generating b.out, it accepts this directive but ignores it.

Node:Double, Next:, Previous:Dim, Up:Pseudo Ops

.double flonums

.double expects zero or more flonums, separated by commas. It assembles floating point numbers. The exact kind of floating point numbers emitted depends on how as is configured. See Machine Dependencies.

Node:Eject, Next:, Previous:Double, Up:Pseudo Ops

.eject

Force a page break at this point, when generating assembly listings.

Node:Else, Next:, Previous:Eject, Up:Pseudo Ops

.else

.else is part of the as support for conditional assembly; see .if. It marks the beginning of a section of code to be assembled if the condition for the preceding .if was false.

Node:Elseif, Next:, Previous:Else, Up:Pseudo Ops

.elseif

.elseif is part of the as support for conditional assembly; see .if. It is shorthand for beginning a new .if block that would otherwise fill the entire .else section.

Node:End, Next:, Previous:Elseif, Up:Pseudo Ops

.end

.end marks the end of the assembly file. as does not process anything in the file past the .end directive.

Node:Endef, Next:, Previous:End, Up:Pseudo Ops

.endef

This directive flags the end of a symbol definition begun with .def.

.endef is only meaningful when generating COFF format output; if as is configured to generate b.out, it accepts this directive but ignores it.

Node:Endfunc, Next:, Previous:Endef, Up:Pseudo Ops

.endfunc

.endfunc marks the end of a function specified with .func.

Node:Endif, Next:, Previous:Endfunc, Up:Pseudo Ops

.endif

.endif is part of the as support for conditional assembly; it marks the end of a block of code that is only assembled conditionally. See .if.

Node:Equ, Next:, Previous:Endif, Up:Pseudo Ops

.equ symbol, expression

This directive sets the value of symbol to expression. It is synonymous with .set; see .set.

The syntax for equ on the HPPA is symbol .equ expression.

Node:Equiv, Next:, Previous:Equ, Up:Pseudo Ops

.equiv symbol, expression

The .equiv directive is like .equ and .set, except that the assembler will signal an error if symbol is already defined.

Except for the contents of the error message, this is roughly equivalent to 

.ifdef SYM
.err
.endif
.equ SYM,VAL

Node:Err, Next:, Previous:Equiv, Up:Pseudo Ops

.err

If as assembles a .err directive, it will print an error message and, unless the -Z option was used, it will not generate an object file. This can be used to signal error an conditionally compiled code.

Node:Exitm, Next:, Previous:Err, Up:Pseudo Ops

.exitm

Exit early from the current macro definition. See Macro.

Node:Extern, Next:, Previous:Exitm, Up:Pseudo Ops

.extern

.extern is accepted in the source program--for compatibility with other assemblers--but it is ignored. as treats all undefined symbols as external.

Node:Fail, Next:, Previous:Extern, Up:Pseudo Ops

.fail expression

Generates an error or a warning. If the value of the expression is 500 or more, as will print a warning message. If the value is less than 500, as will print an error message. The message will include the value of expression. This can occasionally be useful inside complex nested macros or conditional assembly.

Node:File, Next:, Previous:Fail, Up:Pseudo Ops

.file string

.file tells as that we are about to start a new logical file. string is the new file name. In general, the filename is recognized whether or not it is surrounded by quotes "; but if you wish to specify an empty file name, you must give the quotes-"". This statement may go away in future: it is only recognized to be compatible with old as programs. In some configurations of as, .file has already been removed to avoid conflicts with other assemblers. See Machine Dependencies.

Node:Fill, Next:, Previous:File, Up:Pseudo Ops

.fill repeat , size , value

repeat, size and value are absolute expressions. This emits repeat copies of size bytes. Repeat may be zero or more. Size may be zero or more, but if it is more than 8, then it is deemed to have the value 8, compatible with other people's assemblers. The contents of each repeat bytes is taken from an 8-byte number. The highest order 4 bytes are zero. The lowest order 4 bytes are value rendered in the byte-order of an integer on the computer as is assembling for. Each size bytes in a repetition is taken from the lowest order size bytes of this number. Again, this bizarre behavior is compatible with other people's assemblers.

size and value are optional. If the second comma and value are absent, value is assumed zero. If the first comma and following tokens are absent, size is assumed to be 1.

Node:Float, Next:, Previous:Fill, Up:Pseudo Ops

.float flonums

This directive assembles zero or more flonums, separated by commas. It has the same effect as .single. The exact kind of floating point numbers emitted depends on how as is configured. See Machine Dependencies.

Node:Func, Next:, Previous:Float, Up:Pseudo Ops

.func name[,label]

.func emits debugging information to denote function name, and is ignored unless the file is assembled with debugging enabled. Only --gstabs is currently supported. label is the entry point of the function and if omitted name prepended with the leading char is used. leading char is usually _ or nothing, depending on the target. All functions are currently defined to have void return type. The function must be terminated with .endfunc.

Node:Global, Next:, Previous:Func, Up:Pseudo Ops

.global symbol, .globl symbol

.global makes the symbol visible to ld. If you define symbol in your partial program, its value is made available to other partial programs that are linked with it. Otherwise, symbol takes its attributes from a symbol of the same name from another file linked into the same program.

Both spellings (.globl and .global) are accepted, for compatibility with other assemblers.

On the HPPA, .global is not always enough to make it accessible to other partial programs. You may need the HPPA-only .EXPORT directive as well. See HPPA Assembler Directives.

Node:Hidden, Next:, Previous:Global, Up:Pseudo Ops

.hidden names

This one of the ELF visibility directives. The other two are .internal (see .internal) and .protected (see .protected).

This directive overrides the named symbols default visibility (which is set by their binding: local, global or weak). The directive sets the visibility to hidden which means that the symbols are not visible to other components. Such symbols are always considered to be protected as well.

Node:hword, Next:, Previous:Hidden, Up:Pseudo Ops

.hword expressions

This expects zero or more expressions, and emits a 16 bit number for each.

This directive is a synonym for .short; depending on the target architecture, it may also be a synonym for .word.

Node:Ident, Next:, Previous:hword, Up:Pseudo Ops

.ident

This directive is used by some assemblers to place tags in object files. as simply accepts the directive for source-file compatibility with such assemblers, but does not actually emit anything for it.

Node:If, Next:, Previous:Ident, Up:Pseudo Ops

.if absolute expression

.if marks the beginning of a section of code which is only considered part of the source program being assembled if the argument (which must be an absolute expression) is non-zero. The end of the conditional section of code must be marked by .endif (see .endif); optionally, you may include code for the alternative condition, flagged by .else (see .else). If you have several conditions to check, .elseif may be used to avoid nesting blocks if/else within each subsequent .else block.

The following variants of .if are also supported:

.ifdef symbol
Assembles the following section of code if the specified symbol has been defined.
.ifc string1,string2
Assembles the following section of code if the two strings are the same. The strings may be optionally quoted with single quotes. If they are not quoted, the first string stops at the first comma, and the second string stops at the end of the line. Strings which contain whitespace should be quoted. The string comparison is case sensitive.
.ifeq absolute expression
Assembles the following section of code if the argument is zero.
.ifeqs string1,string2
Another form of .ifc. The strings must be quoted using double quotes.
.ifge absolute expression
Assembles the following section of code if the argument is greater than or equal to zero.
.ifgt absolute expression
Assembles the following section of code if the argument is greater than zero.
.ifle absolute expression
Assembles the following section of code if the argument is less than or equal to zero.
.iflt absolute expression
Assembles the following section of code if the argument is less than zero.
.ifnc string1,string2.
Like .ifc, but the sense of the test is reversed: this assembles the following section of code if the two strings are not the same.
.ifndef symbol
.ifnotdef symbol
Assembles the following section of code if the specified symbol has not been defined. Both spelling variants are equivalent.
.ifne absolute expression
Assembles the following section of code if the argument is not equal to zero (in other words, this is equivalent to .if).
.ifnes string1,string2
Like .ifeqs, but the sense of the test is reversed: this assembles the following section of code if the two strings are not the same.

Node:Incbin, Next:, Previous:If, Up:Pseudo Ops

.incbin "file"[,skip[,count]]

The incbin directive includes file verbatim at the current location. You can control the search paths used with the -I command-line option (see Command-Line Options). Quotation marks are required around file.

The skip argument skips a number of bytes from the start of the file. The count argument indicates the maximum number of bytes to read. Note that the data is not aligned in any way, so it is the user's responsibility to make sure that proper alignment is provided both before and after the incbin directive.

Node:Include, Next:, Previous:Incbin, Up:Pseudo Ops

.include "file"

This directive provides a way to include supporting files at specified points in your source program. The code from file is assembled as if it followed the point of the .include; when the end of the included file is reached, assembly of the original file continues. You can control the search paths used with the -I command-line option (see Command-Line Options). Quotation marks are required around file.

Node:Int, Next:, Previous:Include, Up:Pseudo Ops

.int expressions

Expect zero or more expressions, of any section, separated by commas. For each expression, emit a number that, at run time, is the value of that expression. The byte order and bit size of the number depends on what kind of target the assembly is for.

Node:Internal, Next:, Previous:Int, Up:Pseudo Ops

.internal names

This one of the ELF visibility directives. The other two are .hidden (see .hidden) and .protected (see .protected).

This directive overrides the named symbols default visibility (which is set by their binding: local, global or weak). The directive sets the visibility to internal which means that the symbols are considered to be hidden (ie not visible to other components), and that some extra, processor specific processing must also be performed upon the symbols as well.

Node:Irp, Next:, Previous:Internal, Up:Pseudo Ops

.irp symbol,values...

Evaluate a sequence of statements assigning different values to symbol. The sequence of statements starts at the .irp directive, and is terminated by an .endr directive. For each value, symbol is set to value, and the sequence of statements is assembled. If no value is listed, the sequence of statements is assembled once, with symbol set to the null string. To refer to symbol within the sequence of statements, use \symbol.

For example, assembling 

        .irp    param,1,2,3
        move    d\param,sp@-
        .endr

is equivalent to assembling 

        move    d1,sp@-
        move    d2,sp@-
        move    d3,sp@-

Node:Irpc, Next:, Previous:Irp, Up:Pseudo Ops

.irpc symbol,values...

Evaluate a sequence of statements assigning different values to symbol. The sequence of statements starts at the .irpc directive, and is terminated by an .endr directive. For each character in value, symbol is set to the character, and the sequence of statements is assembled. If no value is listed, the sequence of statements is assembled once, with symbol set to the null string. To refer to symbol within the sequence of statements, use \symbol.

For example, assembling 

        .irpc    param,123
        move    d\param,sp@-
        .endr

is equivalent to assembling 

        move    d1,sp@-
        move    d2,sp@-
        move    d3,sp@-

Node:Lcomm, Next:, Previous:Irpc, Up:Pseudo Ops

.lcomm symbol , length

Reserve length (an absolute expression) bytes for a local common denoted by symbol. The section and value of symbol are those of the new local common. The addresses are allocated in the bss section, so that at run-time the bytes start off zeroed. Symbol is not declared global (see .global), so is normally not visible to ld.

Some targets permit a third argument to be used with .lcomm. This argument specifies the desired alignment of the symbol in the bss section.

The syntax for .lcomm differs slightly on the HPPA. The syntax is symbol .lcomm, length; symbol is optional.

Node:Lflags, Next:, Previous:Lcomm, Up:Pseudo Ops

.lflags

as accepts this directive, for compatibility with other assemblers, but ignores it.

Node:Line, Next:, Previous:Lflags, Up:Pseudo Ops

.line line-number

Change the logical line number. line-number must be an absolute expression. The next line has that logical line number. Therefore any other statements on the current line (after a statement separator character) are reported as on logical line number line-number - 1. One day as will no longer support this directive: it is recognized only for compatibility with existing assembler programs.

Warning: In the AMD29K configuration of as, this command is not available; use the synonym .ln in that context.

Even though this is a directive associated with the a.out or b.out object-code formats, as still recognizes it when producing COFF output, and treats .line as though it were the COFF .ln if it is found outside a .def/.endef pair.

Inside a .def, .line is, instead, one of the directives used by compilers to generate auxiliary symbol information for debugging.

Node:Linkonce, Next:, Previous:Ln, Up:Pseudo Ops

.linkonce [type]

Mark the current section so that the linker only includes a single copy of it. This may be used to include the same section in several different object files, but ensure that the linker will only include it once in the final output file. The .linkonce pseudo-op must be used for each instance of the section. Duplicate sections are detected based on the section name, so it should be unique.

This directive is only supported by a few object file formats; as of this writing, the only object file format which supports it is the Portable Executable format used on Windows NT.

The type argument is optional. If specified, it must be one of the following strings. For example: 

.linkonce same_size
Not all types may be supported on all object file formats.
discard
Silently discard duplicate sections. This is the default.
one_only
Warn if there are duplicate sections, but still keep only one copy.
same_size
Warn if any of the duplicates have different sizes.
same_contents
Warn if any of the duplicates do not have exactly the same contents.

Node:Ln, Next:, Previous:Line, Up:Pseudo Ops

.ln line-number

.ln is a synonym for .line.

Node:MRI, Next:, Previous:Macro, Up:Pseudo Ops

.mri val

If val is non-zero, this tells as to enter MRI mode. If val is zero, this tells as to exit MRI mode. This change affects code assembled until the next .mri directive, or until the end of the file. See MRI mode.

Node:List, Next:, Previous:Linkonce, Up:Pseudo Ops

.list

Control (in conjunction with the .nolist directive) whether or not assembly listings are generated. These two directives maintain an internal counter (which is zero initially). .list increments the counter, and .nolist decrements it. Assembly listings are generated whenever the counter is greater than zero.

By default, listings are disabled. When you enable them (with the -a command line option; see Command-Line Options), the initial value of the listing counter is one.

Node:Long, Next:, Previous:List, Up:Pseudo Ops

.long expressions

.long is the same as .int, see .int.

Node:Macro, Next:, Previous:Long, Up:Pseudo Ops

.macro

The commands .macro and .endm allow you to define macros that generate assembly output. For example, this definition specifies a macro sum that puts a sequence of numbers into memory: 

        .macro  sum from=0, to=5
        .long   \from
        .if     \to-\from
        sum     "(\from+1)",\to
        .endif
        .endm

With that definition, SUM 0,5 is equivalent to this assembly input: 

        .long   0
        .long   1
        .long   2
        .long   3
        .long   4
        .long   5
.macro macname
.macro macname macargs ...
Begin the definition of a macro called macname. If your macro definition requires arguments, specify their names after the macro name, separated by commas or spaces. You can supply a default value for any macro argument by following the name with =deflt. For example, these are all valid .macro statements:
.macro comm
Begin the definition of a macro called comm, which takes no arguments.
.macro plus1 p, p1
.macro plus1 p p1
Either statement begins the definition of a macro called plus1, which takes two arguments; within the macro definition, write \p or \p1 to evaluate the arguments.
.macro reserve_str p1=0 p2
Begin the definition of a macro called reserve_str, with two arguments. The first argument has a default value, but not the second. After the definition is complete, you can call the macro either as reserve_str a,b (with \p1 evaluating to a and \p2 evaluating to b), or as reserve_str ,b (with \p1 evaluating as the default, in this case 0, and \p2 evaluating to b).

When you call a macro, you can specify the argument values either by position, or by keyword. For example, sum 9,17 is equivalent to sum to=17, from=9.

.endm
Mark the end of a macro definition.
.exitm
Exit early from the current macro definition.
\@
as maintains a counter of how many macros it has executed in this pseudo-variable; you can copy that number to your output with \@, but only within a macro definition.

Node:Nolist, Next:, Previous:MRI, Up:Pseudo Ops

.nolist

Control (in conjunction with the .list directive) whether or not assembly listings are generated. These two directives maintain an internal counter (which is zero initially). .list increments the counter, and .nolist decrements it. Assembly listings are generated whenever the counter is greater than zero.

Node:Octa, Next:, Previous:Nolist, Up:Pseudo Ops

.octa bignums

This directive expects zero or more bignums, separated by commas. For each bignum, it emits a 16-byte integer.

The term "octa" comes from contexts in which a "word" is two bytes; hence octa-word for 16 bytes.

Node:Org, Next:, Previous:Octa, Up:Pseudo Ops

.org new-lc , fill

Advance the location counter of the current section to new-lc. new-lc is either an absolute expression or an expression with the same section as the current subsection. That is, you can't use .org to cross sections: if new-lc has the wrong section, the .org directive is ignored. To be compatible with former assemblers, if the section of new-lc is absolute, as issues a warning, then pretends the section of new-lc is the same as the current subsection.

.org may only increase the location counter, or leave it unchanged; you cannot use .org to move the location counter backwards.

Because as tries to assemble programs in one pass, new-lc may not be undefined. If you really detest this restriction we eagerly await a chance to share your improved assembler.

Beware that the origin is relative to the start of the section, not to the start of the subsection. This is compatible with other people's assemblers.

When the location counter (of the current subsection) is advanced, the intervening bytes are filled with fill which should be an absolute expression. If the comma and fill are omitted, fill defaults to zero.

Node:P2align, Next:, Previous:Org, Up:Pseudo Ops

.p2align[wl] abs-expr, abs-expr, abs-expr

Pad the location counter (in the current subsection) to a particular storage boundary. The first expression (which must be absolute) is the number of low-order zero bits the location counter must have after advancement. For example .p2align 3 advances the location counter until it a multiple of 8. If the location counter is already a multiple of 8, no change is needed.

The second expression (also absolute) gives the fill value to be stored in the padding bytes. It (and the comma) may be omitted. If it is omitted, the padding bytes are normally zero. However, on some systems, if the section is marked as containing code and the fill value is omitted, the space is filled with no-op instructions.

The third expression is also absolute, and is also optional. If it is present, it is the maximum number of bytes that should be skipped by this alignment directive. If doing the alignment would require skipping more bytes than the specified maximum, then the alignment is not done at all. You can omit the fill value (the second argument) entirely by simply using two commas after the required alignment; this can be useful if you want the alignment to be filled with no-op instructions when appropriate.

The .p2alignw and .p2alignl directives are variants of the .p2align directive. The .p2alignw directive treats the fill pattern as a two byte word value. The .p2alignl directives treats the fill pattern as a four byte longword value. For example, .p2alignw 2,0x368d will align to a multiple of 4. If it skips two bytes, they will be filled in with the value 0x368d (the exact placement of the bytes depends upon the endianness of the processor). If it skips 1 or 3 bytes, the fill value is undefined.

Node:Previous, Next:, Previous:PopSection, Up:Pseudo Ops

.previous

This is one of the ELF section stack manipulation directives. The others are .section (see Section), .subsection (see SubSection), .pushsection (see PushSection), and .popsection (see PopSection).

This directive swaps the current section (and subsection) with most recently referenced section (and subsection) prior to this one. Multiple .previous directives in a row will flip between two sections (and their subsections).

In terms of the section stack, this directive swaps the current section with the top section on the section stack.

Node:PopSection, Next:, Previous:P2align, Up:Pseudo Ops

.popsection

This is one of the ELF section stack manipulation directives. The others are .section (see Section), .subsection (see SubSection), .pushsection (see PushSection), and .previous (see Previous).

This directive replaces the current section (and subsection) with the top section (and subsection) on the section stack. This section is popped off the stack.

Node:Print, Next:, Previous:Previous, Up:Pseudo Ops

.print string

as will print string on the standard output during assembly. You must put string in double quotes.

Node:Protected, Next:, Previous:Print, Up:Pseudo Ops

.protected names

This one of the ELF visibility directives. The other two are .hidden (see Hidden) and .internal (see Internal).

This directive overrides the named symbols default visibility (which is set by their binding: local, global or weak). The directive sets the visibility to protected which means that any references to the symbols from within the components that defines them must be resolved to the definition in that component, even if a definition in another component would normally preempt this.

Node:Psize, Next:, Previous:Protected, Up:Pseudo Ops

.psize lines , columns

Use this directive to declare the number of lines--and, optionally, the number of columns--to use for each page, when generating listings.

If you do not use .psize, listings use a default line-count of 60. You may omit the comma and columns specification; the default width is 200 columns.

as generates formfeeds whenever the specified number of lines is exceeded (or whenever you explicitly request one, using .eject).

If you specify lines as 0, no formfeeds are generated save those explicitly specified with .eject.

Node:Purgem, Next:, Previous:Psize, Up:Pseudo Ops

.purgem name

Undefine the macro name, so that later uses of the string will not be expanded. See Macro.

Node:PushSection, Next:, Previous:Purgem, Up:Pseudo Ops

.pushsection name , subsection

This is one of the ELF section stack manipulation directives. The others are .section (see Section), .subsection (see SubSection), .popsection (see PopSection), and .previous (see Previous).

This directive is a synonym for .section. It pushes the current section (and subsection) onto the top of the section stack, and then replaces the current section and subsection with name and subsection.

Node:Quad, Next:, Previous:PushSection, Up:Pseudo Ops

.quad bignums

.quad expects zero or more bignums, separated by commas. For each bignum, it emits an 8-byte integer. If the bignum won't fit in 8 bytes, it prints a warning message; and just takes the lowest order 8 bytes of the bignum.

The term "quad" comes from contexts in which a "word" is two bytes; hence quad-word for 8 bytes.

Node:Rept, Next:, Previous:Quad, Up:Pseudo Ops

.rept count

Repeat the sequence of lines between the .rept directive and the next .endr directive count times.

For example, assembling 

        .rept   3
        .long   0
        .endr

is equivalent to assembling 

        .long   0
        .long   0
        .long   0

Node:Sbttl, Next:, Previous:Rept, Up:Pseudo Ops

.sbttl "subheading"

Use subheading as the title (third line, immediately after the title line) when generating assembly listings.

This directive affects subsequent pages, as well as the current page if it appears within ten lines of the top of a page.

Node:Scl, Next:, Previous:Sbttl, Up:Pseudo Ops

.scl class

Set the storage-class value for a symbol. This directive may only be used inside a .def/.endef pair. Storage class may flag whether a symbol is static or external, or it may record further symbolic debugging information.

The .scl directive is primarily associated with COFF output; when configured to generate b.out output format, as accepts this directive but ignores it.

Node:Section, Next:, Previous:Scl, Up:Pseudo Ops

.section name (COFF version)

Use the .section directive to assemble the following code into a section named name.

This directive is only supported for targets that actually support arbitrarily named sections; on a.out targets, for example, it is not accepted, even with a standard a.out section name.

For COFF targets, the .section directive is used in one of the following ways: 

.section name[, "flags"]
.section name[, subsegment]

If the optional argument is quoted, it is taken as flags to use for the section. Each flag is a single character. The following flags are recognized:

b
bss section (uninitialized data)
n
section is not loaded
w
writable section
d
data section
r
read-only section
x
executable section
s
shared section (meaningful for PE targets)

If no flags are specified, the default flags depend upon the section name. If the section name is not recognized, the default will be for the section to be loaded and writable. Note the n and w flags remove attributes from the section, rather than adding them, so if they are used on their own it will be as if no flags had been specified at all.

If the optional argument to the .section directive is not quoted, it is taken as a subsegment number (see Sub-Sections).

.section name (ELF version)

This is one of the ELF section stack manipulation directives. The others are .subsection (see SubSection), .pushsection (see PushSection), .popsection (see PopSection), and .previous (see Previous).

For ELF targets, the .section directive is used like this: 

.section name [, "flags"[, @type]]

The optional flags argument is a quoted string which may contain any combination of the following characters:

a
section is allocatable
w
section is writable
x
section is executable

The optional type argument may contain one of the following constants:

@progbits
section contains data
@nobits
section does not contain data (i.e., section only occupies space)

If no flags are specified, the default flags depend upon the section name. If the section name is not recognized, the default will be for the section to have none of the above flags: it will not be allocated in memory, nor writable, nor executable. The section will contain data.

For ELF targets, the assembler supports another type of .section directive for compatibility with the Solaris assembler: 

.section "name"[, flags...]

Note that the section name is quoted. There may be a sequence of comma separated flags:

#alloc
section is allocatable
#write
section is writable
#execinstr
section is executable

This directive replaces the current section and subsection. The replaced section and subsection are pushed onto the section stack. See the contents of the gas testsuite directory gas/testsuite/gas/elf for some examples of how this directive and the other section stack directives work.

Node:Set, Next:, Previous:Section, Up:Pseudo Ops

.set symbol, expression

Set the value of symbol to expression. This changes symbol's value and type to conform to expression. If symbol was flagged as external, it remains flagged (see Symbol Attributes).

You may .set a symbol many times in the same assembly.

If you .set a global symbol, the value stored in the object file is the last value stored into it.

The syntax for set on the HPPA is symbol .set expression.

Node:Short, Next:, Previous:Set, Up:Pseudo Ops

.short expressions

.short is normally the same as .word. See .word.

In some configurations, however, .short and .word generate numbers of different lengths; see Machine Dependencies.

Node:Single, Next:, Previous:Short, Up:Pseudo Ops

.single flonums

This directive assembles zero or more flonums, separated by commas. It has the same effect as .float. The exact kind of floating point numbers emitted depends on how as is configured. See Machine Dependencies.

Node:Size, Next:, Previous:Single, Up:Pseudo Ops

.size (COFF version)

This directive is generated by compilers to include auxiliary debugging information in the symbol table. It is only permitted inside .def/.endef pairs.

.size is only meaningful when generating COFF format output; when as is generating b.out, it accepts this directive but ignores it.

.size name , expression (ELF version)

This directive is used to set the size associated with a symbol name. The size in bytes is computed from expression which can make use of label arithmetic. This directive is typically used to set the size of function symbols.

Node:Sleb128, Next:, Previous:Skip, Up:Pseudo Ops

.sleb128 expressions

sleb128 stands for "signed little endian base 128." This is a compact, variable length representation of numbers used by the DWARF symbolic debugging format. See .uleb128.

Node:Skip, Next:, Previous:Size, Up:Pseudo Ops

.skip size , fill

This directive emits size bytes, each of value fill. Both size and fill are absolute expressions. If the comma and fill are omitted, fill is assumed to be zero. This is the same as .space.

Node:Space, Next:, Previous:Sleb128, Up:Pseudo Ops

.space size , fill

This directive emits size bytes, each of value fill. Both size and fill are absolute expressions. If the comma and fill are omitted, fill is assumed to be zero. This is the same as .skip.

Warning: .space has a completely different meaning for HPPA targets; use .block as a substitute. See HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001) for the meaning of the .space directive. See HPPA Assembler Directives, for a summary.

On the AMD 29K, this directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.

Warning: In most versions of the GNU assembler, the directive .space has the effect of .block See Machine Dependencies.

Node:Stab, Next:, Previous:Space, Up:Pseudo Ops

.stabd, .stabn, .stabs

There are three directives that begin .stab. All emit symbols (see Symbols), for use by symbolic debuggers. The symbols are not entered in the as hash table: they cannot be referenced elsewhere in the source file. Up to five fields are required:

string
This is the symbol's name. It may contain any character except \000, so is more general than ordinary symbol names. Some debuggers used to code arbitrarily complex structures into symbol names using this field.
type
An absolute expression. The symbol's type is set to the low 8 bits of this expression. Any bit pattern is permitted, but ld and debuggers choke on silly bit patterns.
other
An absolute expression. The symbol's "other" attribute is set to the low 8 bits of this expression.
desc
An absolute expression. The symbol's descriptor is set to the low 16 bits of this expression.
value
An absolute expression which becomes the symbol's value.

If a warning is detected while reading a .stabd, .stabn, or .stabs statement, the symbol has probably already been created; you get a half-formed symbol in your object file. This is compatible with earlier assemblers!

.stabd type , other , desc
The "name" of the symbol generated is not even an empty string. It is a null pointer, for compatibility. Older assemblers used a null pointer so they didn't waste space in object files with empty strings.

The symbol's value is set to the location counter, relocatably. When your program is linked, the value of this symbol is the address of the location counter when the .stabd was assembled.

.stabn type , other , desc , value
The name of the symbol is set to the empty string "".
.stabs string , type , other , desc , value
All five fields are specified.

Node:String, Next:, Previous:Stab, Up:Pseudo Ops

.string "str"

Copy the characters in str to the object file. You may specify more than one string to copy, separated by commas. Unless otherwise specified for a particular machine, the assembler marks the end of each string with a 0 byte. You can use any of the escape sequences described in Strings.

Node:Struct, Next:, Previous:String, Up:Pseudo Ops

.struct expression

Switch to the absolute section, and set the section offset to expression, which must be an absolute expression. You might use this as follows: 

        .struct 0
field1:
        .struct field1 + 4
field2:
        .struct field2 + 4
field3:
This would define the symbol field1 to have the value 0, the symbol field2 to have the value 4, and the symbol field3 to have the value 8. Assembly would be left in the absolute section, and you would need to use a .section directive of some sort to change to some other section before further assembly.

Node:SubSection, Next:, Previous:Struct, Up:Pseudo Ops

.subsection name

This is one of the ELF section stack manipulation directives. The others are .section (see Section), .pushsection (see PushSection), .popsection (see PopSection), and .previous (see Previous).

This directive replaces the current subsection with name. The current section is not changed. The replaced subsection is put onto the section stack in place of the then current top of stack subsection.

Node:Symver, Next:, Previous:SubSection, Up:Pseudo Ops

.symver

Use the .symver directive to bind symbols to specific version nodes within a source file. This is only supported on ELF platforms, and is typically used when assembling files to be linked into a shared library. There are cases where it may make sense to use this in objects to be bound into an application itself so as to override a versioned symbol from a shared library.

For ELF targets, the .symver directive can be used like this: 

.symver name, name2@nodename
If the symbol name is defined within the file being assembled, the .symver directive effectively creates a symbol alias with the name name2@nodename, and in fact the main reason that we just don't try and create a regular alias is that the @ character isn't permitted in symbol names. The name2 part of the name is the actual name of the symbol by which it will be externally referenced. The name name itself is merely a name of convenience that is used so that it is possible to have definitions for multiple versions of a function within a single source file, and so that the compiler can unambiguously know which version of a function is being mentioned. The nodename portion of the alias should be the name of a node specified in the version script supplied to the linker when building a shared library. If you are attempting to override a versioned symbol from a shared library, then nodename should correspond to the nodename of the symbol you are trying to override.

If the symbol name is not defined within the file being assembled, all references to name will be changed to name2@nodename. If no reference to name is made, name2@nodename will be removed from the symbol table.

Another usage of the .symver directive is: 

.symver name, name2@@nodename
In this case, the symbol name must exist and be defined within the file being assembled. It is similar to name2@nodename. The difference is name2@@nodename will also be used to resolve references to name2 by the linker.

The third usage of the .symver directive is: 

.symver name, name2@@@nodename
When name is not defined within the file being assembled, it is treated as name2@nodename. When name is defined within the file being assembled, the symbol name, name, will be changed to name2@@nodename.

Node:Tag, Next:, Previous:Symver, Up:Pseudo Ops

.tag structname

This directive is generated by compilers to include auxiliary debugging information in the symbol table. It is only permitted inside .def/.endef pairs. Tags are used to link structure definitions in the symbol table with instances of those structures.

.tag is only used when generating COFF format output; when as is generating b.out, it accepts this directive but ignores it.

Node:Text, Next:, Previous:Tag, Up:Pseudo Ops

.text subsection

Tells as to assemble the following statements onto the end of the text subsection numbered subsection, which is an absolute expression. If subsection is omitted, subsection number zero is used.

Node:Title, Next:, Previous:Text, Up:Pseudo Ops

.title "heading"

Use heading as the title (second line, immediately after the source file name and pagenumber) when generating assembly listings.

This directive affects subsequent pages, as well as the current page if it appears within ten lines of the top of a page.

Node:Type, Next:, Previous:Title, Up:Pseudo Ops

.type int (COFF version)

This directive, permitted only within .def/.endef pairs, records the integer int as the type attribute of a symbol table entry.

.type is associated only with COFF format output; when as is configured for b.out output, it accepts this directive but ignores it.

.type name , type description (ELF version)

This directive is used to set the type of symbol name to be either a function symbol or an object symbol. There are five different syntaxes supported for the type description field, in order to provide compatibility with various other assemblers. The syntaxes supported are: 

  .type <name>,#function
  .type <name>,#object

  .type <name>,@function
  .type <name>,@object

  .type <name>,%function
  .type <name>,%object

  .type <name>,"function"
  .type <name>,"object"

  .type <name> STT_FUNCTION
  .type <name> STT_OBJECT

Node:Uleb128, Next:, Previous:Type, Up:Pseudo Ops

.uleb128 expressions

uleb128 stands for "unsigned little endian base 128." This is a compact, variable length representation of numbers used by the DWARF symbolic debugging format. See .sleb128.

Node:Val, Next:, Previous:Uleb128, Up:Pseudo Ops

.val addr

This directive, permitted only within .def/.endef pairs, records the address addr as the value attribute of a symbol table entry.

.val is used only for COFF output; when as is configured for b.out, it accepts this directive but ignores it.

Node:Version, Next:, Previous:Val, Up:Pseudo Ops

.version "string"

This directive creates a .note section and places into it an ELF formatted note of type NT_VERSION. The note's name is set to string.

Node:VTableEntry, Next:, Previous:Version, Up:Pseudo Ops

.vtable_entry table, offset

This directive finds or creates a symbol table and creates a VTABLE_ENTRY relocation for it with an addend of offset.

Node:VTableInherit, Next:, Previous:VTableEntry, Up:Pseudo Ops

.vtable_inherit child, parent

This directive finds the symbol child and finds or creates the symbol parent and then creates a VTABLE_INHERIT relocation for the parent whose addend is the value of the child symbol. As a special case the parent name of 0 is treated as refering the *ABS* section.

Node:Weak, Next:, Previous:VTableInherit, Up:Pseudo Ops

.weak names

This directive sets the weak attribute on the comma separated list of symbol names. If the symbols do not already exist, they will be created.

Node:Word, Next:, Previous:Weak, Up:Pseudo Ops

.word expressions

This directive expects zero or more expressions, of any section, separated by commas.

The size of the number emitted, and its byte order, depend on what target computer the assembly is for.

Warning: Special Treatment to support Compilers

Machines with a 32-bit address space, but that do less than 32-bit addressing, require the following special treatment. If the machine of interest to you does 32-bit addressing (or doesn't require it; see Machine Dependencies), you can ignore this issue.

In order to assemble compiler output into something that works, as occasionally does strange things to .word directives. Directives of the form .word sym1-sym2 are often emitted by compilers as part of jump tables. Therefore, when as assembles a directive of the form .word sym1-sym2, and the difference between sym1 and sym2 does not fit in 16 bits, as creates a secondary jump table, immediately before the next label. This secondary jump table is preceded by a short-jump to the first byte after the secondary table. This short-jump prevents the flow of control from accidentally falling into the new table. Inside the table is a long-jump to sym2. The original .word contains sym1 minus the address of the long-jump to sym2.

If there were several occurrences of .word sym1-sym2 before the secondary jump table, all of them are adjusted. If there was a .word sym3-sym4, that also did not fit in sixteen bits, a long-jump to sym4 is included in the secondary jump table, and the .word directives are adjusted to contain sym3 minus the address of the long-jump to sym4; and so on, for as many entries in the original jump table as necessary.

Node:Deprecated, Previous:Word, Up:Pseudo Ops

Deprecated Directives

One day these directives won't work. They are included for compatibility with older assemblers.

.abort
.line

Node:Machine Dependencies, Next:, Previous:Pseudo Ops, Up:Top

Machine Dependent Features

The machine instruction sets are (almost by definition) different on each machine where as runs. Floating point representations vary as well, and as often supports a few additional directives or command-line options for compatibility with other assemblers on a particular platform. Finally, some versions of as support special pseudo-instructions for branch optimization.

This chapter discusses most of these differences, though it does not include details on any machine's instruction set. For details on that subject, see the hardware manufacturer's manual.

Node:ARC-Dependent, Next:, Previous:AMD29K-Dependent, Up:Machine Dependencies

ARC Dependent Features

Node:ARC Options, Next:, Up:ARC-Dependent

Options


-marc[5|6|7|8]
This option selects the core processor variant. Using -marc is the same as -marc6, which is also the default.

arc5
Base instruction set.
arc6
Jump-and-link (jl) instruction. No requirement of an instruction between setting flags and conditional jump. For example: 
  mov.f r0,r1
  beq   foo

arc7
Break (brk) and sleep (sleep) instructions.
arc8
Software interrupt (swi) instruction.

Note: the .option directive can to be used to select a core variant from within assembly code.

-EB
This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.
-EL
This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor - this is the default.

Node:ARC Syntax, Next:, Previous:ARC Options, Up:ARC-Dependent

Syntax

Node:ARC-Chars, Next:, Up:ARC Syntax

Special Characters

*TODO*

Node:ARC-Regs, Previous:ARC-Chars, Up:ARC Syntax

Register Names

*TODO*

Node:ARC Floating Point, Next:, Previous:ARC Syntax, Up:ARC-Dependent

Floating Point

The ARC core does not currently have hardware floating point support. Software floating point support is provided by GCC and uses IEEE floating-point numbers.

Node:ARC Directives, Next:, Previous:ARC Floating Point, Up:ARC-Dependent

ARC Machine Directives

The ARC version of as supports the following additional machine directives:


.2byte expressions
*TODO*
.3byte expressions
*TODO*
.4byte expressions
*TODO*
.extAuxRegister name,address,mode
*TODO* 
  .extAuxRegister mulhi,0x12,w

.extCondCode suffix,value
*TODO* 
  .extCondCode is_busy,0x14

.extCoreRegister name,regnum,mode,shortcut
*TODO* 
  .extCoreRegister mlo,57,r,can_shortcut

.extInstruction name,opcode,subopcode,suffixclass,syntaxclass
*TODO* 
  .extInstruction mul64,0x14,0x0,SUFFIX_COND,SYNTAX_3OP|OP1_MUST_BE_IMM

.half expressions
*TODO*
.long expressions
*TODO*
.option arc|arc5|arc6|arc7|arc8
The .option directive must be followed by the desired core version. Again arc is an alias for arc6.

Note: the .option directive overrides the command line option -marc; a warning is emitted when the version is not consistent between the two - even for the implicit default core version (arc6).

.short expressions
*TODO*
.word expressions
*TODO*

Node:ARC Opcodes, Previous:ARC Directives, Up:ARC-Dependent

Opcodes

For information on the ARC instruction set, see ARC Programmers Reference Manual, ARC Cores Ltd.

Node:AMD29K-Dependent, Next:, Up:Machine Dependencies

AMD 29K Dependent Features

Node:AMD29K Options, Next:, Up:AMD29K-Dependent

Options

as has no additional command-line options for the AMD 29K family.

Node:AMD29K Syntax, Next:, Previous:AMD29K Options, Up:AMD29K-Dependent

Syntax

Node:AMD29K-Macros, Next:, Up:AMD29K Syntax

Macros

The macro syntax used on the AMD 29K is like that described in the AMD 29K Family Macro Assembler Specification. Normal as macros should still work.

Node:AMD29K-Chars, Next:, Previous:AMD29K-Macros, Up:AMD29K Syntax

Special Characters

; is the line comment character.

The character ? is permitted in identifiers (but may not begin an identifier).

Node:AMD29K-Regs, Previous:AMD29K-Chars, Up:AMD29K Syntax

Register Names

General-purpose registers are represented by predefined symbols of the form GRnnn (for global registers) or LRnnn (for local registers), where nnn represents a number between 0 and 127, written with no leading zeros. The leading letters may be in either upper or lower case; for example, gr13 and LR7 are both valid register names.

You may also refer to general-purpose registers by specifying the register number as the result of an expression (prefixed with %% to flag the expression as a register number): 

%%expression

--where expression must be an absolute expression evaluating to a number between 0 and 255. The range [0, 127] refers to global registers, and the range [128, 255] to local registers.

In addition, as understands the following protected special-purpose register names for the AMD 29K family: 

  vab    chd    pc0
  ops    chc    pc1
  cps    rbp    pc2
  cfg    tmc    mmu
  cha    tmr    lru

These unprotected special-purpose register names are also recognized: 

  ipc    alu    fpe
  ipa    bp     inte
  ipb    fc     fps
  q      cr     exop

Node:AMD29K Floating Point, Next:, Previous:AMD29K Syntax, Up:AMD29K-Dependent

Floating Point

The AMD 29K family uses IEEE floating-point numbers.

Node:AMD29K Directives, Next:, Previous:AMD29K Floating Point, Up:AMD29K-Dependent

AMD 29K Machine Directives

.block size , fill
This directive emits size bytes, each of value fill. Both size and fill are absolute expressions. If the comma and fill are omitted, fill is assumed to be zero.

In other versions of the GNU assembler, this directive is called .space.

.cputype
This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.
.file
This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.
Warning: in other versions of the GNU assembler, .file is used for the directive called .app-file in the AMD 29K support.

.line
This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.
.sect
This directive is ignored; it is accepted for compatibility with other AMD 29K assemblers.
.use section name
Establishes the section and subsection for the following code; section name may be one of .text, .data, .data1, or .lit. With one of the first three section name options, .use is equivalent to the machine directive section name; the remaining case, .use .lit, is the same as .data 200.

Node:AMD29K Opcodes, Previous:AMD29K Directives, Up:AMD29K-Dependent

Opcodes

as implements all the standard AMD 29K opcodes. No additional pseudo-instructions are needed on this family.

For information on the 29K machine instruction set, see Am29000 User's Manual, Advanced Micro Devices, Inc.

Node:ARM-Dependent, Next:, Previous:ARC-Dependent, Up:Machine Dependencies

ARM Dependent Features

Node:ARM Options, Next:, Up:ARM-Dependent

Options


-marm[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920|strongarm|strongarm110|strongarm1100]
-mxscale
This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor.
-marmv[2|2a|3|3m|4|4t|5|5t|5te]
This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The option -marmv5te specifies that v5t architecture should be used with the El Segundo extensions enabled.
-mthumb
This option specifies that only Thumb instructions should be assembled.
-mall
This option specifies that any Arm or Thumb instruction should be assembled.
-mfpa [10|11]
This option specifies the floating point architecture in use on the target processor.
-mfpe-old
Do not allow the assembly of floating point multiple instructions.
-mno-fpu
Do not allow the assembly of any floating point instructions.
-mthumb-interwork
This option specifies that the output generated by the assembler should be marked as supporting interworking.
-mapcs [26|32]
This option specifies that the output generated by the assembler should be marked as supporting the indicated version of the Arm Procedure. Calling Standard.
-matpcs
This option specifies that the output generated by the assembler should be marked as supporting the Arm/Thumb Procedure Calling Standard. If enabled this option will cause the assembler to create an empty debugging section in the object file called .arm.atpcs. Debuggers can use this to determine the ABI being used by.
-mapcs-float
This indicates the the floating point variant of the APCS should be used. In this variant floating point arguments are passed in FP registers rather than integer registers.
-mapcs-reentrant
This indicates that the reentrant variant of the APCS should be used. This variant supports position independent code.
-EB
This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.
-EL
This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.
-k
This option specifies that the output of the assembler should be marked as position-independent code (PIC).
-moabi
This indicates that the code should be assembled using the old ARM ELF conventions, based on a beta release release of the ARM-ELF specifications, rather than the default conventions which are based on the final release of the ARM-ELF specifications.

Node:ARM Syntax, Next:, Previous:ARM Options, Up:ARM-Dependent

Syntax

Node:ARM-Chars, Next:, Up:ARM Syntax

Special Characters

The presence of a @ on a line indicates the start of a comment that extends to the end of the current line. If a # appears as the first character of a line, the whole line is treated as a comment.

The ; character can be used instead of a newline to separate statements.

Either # or $ can be used to indicate immediate operands.

*TODO* Explain about /data modifier on symbols.

Node:ARM-Regs, Previous:ARM-Chars, Up:ARM Syntax

Register Names

*TODO* Explain about ARM register naming, and the predefined names.

Node:ARM Floating Point, Next:, Previous:ARM Syntax, Up:ARM-Dependent

Floating Point

The ARM family uses IEEE floating-point numbers.

Node:ARM Directives, Next:, Previous:ARM Floating Point, Up:ARM-Dependent

ARM Machine Directives


.align expression [, expression]
This is the generic .align directive. For the ARM however if the first argument is zero (ie no alignment is needed) the assembler will behave as if the argument had been 2 (ie pad to the next four byte boundary). This is for compatability with ARM's own assembler.
name .req register name
This creates an alias for register name called name. For example: 
        foo .req r0

.code [16|32]
This directive selects the instruction set being generated. The value 16 selects Thumb, with the value 32 selecting ARM.
.thumb
This performs the same action as .code 16.
.arm
This performs the same action as .code 32.
.force_thumb
This directive forces the selection of Thumb instructions, even if the target processor does not support those instructions
.thumb_func
This directive specifies that the following symbol is the name of a Thumb encoded function. This information is necessary in order to allow the assembler and linker to generate correct code for interworking between Arm and Thumb instructions and should be used even if interworking is not going to be performed. The presence of this directive also implies .thumb
.thumb_set
This performs the equivalent of a .set directive in that it creates a symbol which is an alias for another symbol (possibly not yet defined). This directive also has the added property in that it marks the aliased symbol as being a thumb function entry point, in the same way that the .thumb_func directive does.
.ltorg
This directive causes the current contents of the literal pool to be dumped into the current section (which is assumed to be the .text section) at the current location (aligned to a word boundary).
.pool
This is a synonym for .ltorg.

Node:ARM Opcodes, Previous:ARM Directives, Up:ARM-Dependent

Opcodes

as implements all the standard ARM opcodes. It also implements several pseudo opcodes, including several synthetic load instructions.


NOP 
  nop

This pseudo op will always evaluate to a legal ARM instruction that does nothing. Currently it will evaluate to MOV r0, r0.

LDR 
  ldr <register> , = <expression>

If expression evaluates to a numeric constant then a MOV or MVN instruction will be used in place of the LDR instruction, if the constant can be generated by either of these instructions. Otherwise the constant will be placed into the nearest literal pool (if it not already there) and a PC relative LDR instruction will be generated.

ADR 
  adr <register> <label>

This instruction will load the address of label into the indicated register. The instruction will evaluate to a PC relative ADD or SUB instruction depending upon where the label is located. If the label is out of range, or if it is not defined in the same file (and section) as the ADR instruction, then an error will be generated. This instruction will not make use of the literal pool.

ADRL 
  adrl <register> <label>

This instruction will load the address of label into the indicated register. The instruction will evaluate to one or two PC relative ADD or SUB instructions depending upon where the label is located. If a second instruction is not needed a NOP instruction will be generated in its place, so that this instruction is always 8 bytes long.

If the label is out of range, or if it is not defined in the same file (and section) as the ADRL instruction, then an error will be generated. This instruction will not make use of the literal pool.

For information on the ARM or Thumb instruction sets, see ARM Software Development Toolkit Reference Manual, Advanced RISC Machines Ltd.

Node:D10V-Dependent, Next:, Previous:ARM-Dependent, Up:Machine Dependencies

D10V Dependent Features

Node:D10V-Opts, Next:, Up:D10V-Dependent

D10V Options

The Mitsubishi D10V version of as has a few machine dependent options.

-O
The D10V can often execute two sub-instructions in parallel. When this option is used, as will attempt to optimize its output by detecting when instructions can be executed in parallel.
--nowarnswap
To optimize execution performance, as will sometimes swap the order of instructions. Normally this generates a warning. When this option is used, no warning will be generated when instructions are swapped.
--gstabs-packing
--no-gstabs-packing
as packs adjacent short instructions into a single packed instruction. --no-gstabs-packing turns instruction packing off if --gstabs is specified as well; --gstabs-packing (the default) turns instruction packing on even when --gstabs is specified.

Node:D10V-Syntax, Next:, Previous:D10V-Opts, Up:D10V-Dependent

Syntax

The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual. The differences are detailed below.

Node:D10V-Size, Next:, Up:D10V-Syntax

Size Modifiers

The D10V version of as uses the instruction names in the D10V Architecture Manual. However, the names in the manual are sometimes ambiguous. There are instruction names that can assemble to a short or long form opcode. How does the assembler pick the correct form? as will always pick the smallest form if it can. When dealing with a symbol that is not defined yet when a line is being assembled, it will always use the long form. If you need to force the assembler to use either the short or long form of the instruction, you can append either .s (short) or .l (long) to it. For example, if you are writing an assembly program and you want to do a branch to a symbol that is defined later in your program, you can write bra.s foo. Objdump and GDB will always append .s or .l to instructions which have both short and long forms.

Node:D10V-Subs, Next:, Previous:D10V-Size, Up:D10V-Syntax

Sub-Instructions

The D10V assembler takes as input a series of instructions, either one-per-line, or in the special two-per-line format described in the next section. Some of these instructions will be short-form or sub-instructions. These sub-instructions can be packed into a single instruction. The assembler will do this automatically. It will also detect when it should not pack instructions. For example, when a label is defined, the next instruction will never be packaged with the previous one. Whenever a branch and link instruction is called, it will not be packaged with the next instruction so the return address will be valid. Nops are automatically inserted when necessary.

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

Node:D10V-Chars, Next:, Previous:D10V-Subs, Up:D10V-Syntax

Special Characters

; and # are the line comment characters. Sub-instructions may be executed in order, in reverse-order, or in parallel. Instructions listed in the standard one-per-line format will be executed sequentially. To specify the executing order, use the following symbols:

->
Sequential with instruction on the left first.
<-
Sequential with instruction on the right first.
||
Parallel
The D10V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line. For example
abs a1 -> abs r0
Execute these sequentially. The instruction on the right is in the right container and is executed second.
abs r0 <- abs a1
Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first.
ld2w r2,@r8+ || mac a0,r0,r7
Execute these in parallel.
ld2w r2,@r8+ ||
mac a0,r0,r7
Two-line format. Execute these in parallel.
ld2w r2,@r8+
mac a0,r0,r7
Two-line format. Execute these sequentially. Assembler will put them in the proper containers.
ld2w r2,@r8+ ->
mac a0,r0,r7
Two-line format. Execute these sequentially. Same as above but second instruction will always go into right container.
Since $ has no special meaning, you may use it in symbol names.

Node:D10V-Regs, Next:, Previous:D10V-Chars, Up:D10V-Syntax

Register Names

You can use the predefined symbols r0 through r15 to refer to the D10V registers. You can also use sp as an alias for r15. The accumulators are a0 and a1. There are special register-pair names that may optionally be used in opcodes that require even-numbered registers. Register names are not case sensitive.

Register Pairs

r0-r1
r2-r3
r4-r5
r6-r7
r8-r9
r10-r11
r12-r13
r14-r15

The D10V also has predefined symbols for these control registers and status bits:

psw
Processor Status Word
bpsw
Backup Processor Status Word
pc
Program Counter
bpc
Backup Program Counter
rpt_c
Repeat Count
rpt_s
Repeat Start address
rpt_e
Repeat End address
mod_s
Modulo Start address
mod_e
Modulo End address
iba
Instruction Break Address
f0
Flag 0
f1
Flag 1
c
Carry flag

Node:D10V-Addressing, Next:, Previous:D10V-Regs, Up:D10V-Syntax

Addressing Modes

as understands the following addressing modes for the D10V. Rn in the following refers to any of the numbered registers, but not the control registers.

Rn
Register direct
@Rn
Register indirect
@Rn+
Register indirect with post-increment
@Rn-
Register indirect with post-decrement
@-SP
Register indirect with pre-decrement
@(disp, Rn)
Register indirect with displacement
addr
PC relative address (for branch or rep).
#imm
Immediate data (the # is optional and ignored)

Node:D10V-Word, Previous:D10V-Addressing, Up:D10V-Syntax

@WORD Modifier

Any symbol followed by @word will be replaced by the symbol's value shifted right by 2. This is used in situations such as loading a register with the address of a function (or any other code fragment). For example, if you want to load a register with the location of the function main then jump to that function, you could do it as follws: 

ldi     r2, main@word
jmp     r2

Node:D10V-Float, Next:, Previous:D10V-Syntax, Up:D10V-Dependent

Floating Point

The D10V has no hardware floating point, but the .float and .double directives generates IEEE floating-point numbers for compatibility with other development tools.

Node:D10V-Opcodes, Previous:D10V-Float, Up:D10V-Dependent

Opcodes

For detailed information on the D10V machine instruction set, see D10V Architecture: A VLIW Microprocessor for Multimedia Applications (Mitsubishi Electric Corp.). as implements all the standard D10V opcodes. The only changes are those described in the section on size modifiers

Node:D30V-Dependent, Next:, Previous:D10V-Dependent, Up:Machine Dependencies

D30V Dependent Features

Node:D30V-Opts, Next:, Up:D30V-Dependent

D30V Options

The Mitsubishi D30V version of as has a few machine dependent options.

-O
The D30V can often execute two sub-instructions in parallel. When this option is used, as will attempt to optimize its output by detecting when instructions can be executed in parallel.
-n
When this option is used, as will issue a warning every time it adds a nop instruction.
-N
When this option is used, as will issue a warning if it needs to insert a nop after a 32-bit multiply before a load or 16-bit multiply instruction.

Node:D30V-Syntax, Next:, Previous:D30V-Opts, Up:D30V-Dependent

Syntax

The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual. The differences are detailed below.

Node:D30V-Size, Next:, Up:D30V-Syntax

Size Modifiers

The D30V version of as uses the instruction names in the D30V Architecture Manual. However, the names in the manual are sometimes ambiguous. There are instruction names that can assemble to a short or long form opcode. How does the assembler pick the correct form? as will always pick the smallest form if it can. When dealing with a symbol that is not defined yet when a line is being assembled, it will always use the long form. If you need to force the assembler to use either the short or long form of the instruction, you can append either .s (short) or .l (long) to it. For example, if you are writing an assembly program and you want to do a branch to a symbol that is defined later in your program, you can write bra.s foo. Objdump and GDB will always append .s or .l to instructions which have both short and long forms.

Node:D30V-Subs, Next:, Previous:D30V-Size, Up:D30V-Syntax

Sub-Instructions

The D30V assembler takes as input a series of instructions, either one-per-line, or in the special two-per-line format described in the next section. Some of these instructions will be short-form or sub-instructions. These sub-instructions can be packed into a single instruction. The assembler will do this automatically. It will also detect when it should not pack instructions. For example, when a label is defined, the next instruction will never be packaged with the previous one. Whenever a branch and link instruction is called, it will not be packaged with the next instruction so the return address will be valid. Nops are automatically inserted when necessary.

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

Node:D30V-Chars, Next:, Previous:D30V-Subs, Up:D30V-Syntax

Special Characters

; and # are the line comment characters. Sub-instructions may be executed in order, in reverse-order, or in parallel. Instructions listed in the standard one-per-line format will be executed sequentially unless you use the -O option.

To specify the executing order, use the following symbols:

->
Sequential with instruction on the left first.
<-
Sequential with instruction on the right first.
||
Parallel

The D30V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line. For example

abs r2,r3 -> abs r4,r5
Execute these sequentially. The instruction on the right is in the right container and is executed second.
abs r2,r3 <- abs r4,r5
Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first.
abs r2,r3 || abs r4,r5
Execute these in parallel.
ldw r2,@(r3,r4) ||
mulx r6,r8,r9
Two-line format. Execute these in parallel.
mulx a0,r8,r9
stw r2,@(r3,r4)
Two-line format. Execute these sequentially unless -O option is used. If the -O option is used, the assembler will determine if the instructions could be done in parallel (the above two instructions can be done in parallel), and if so, emit them as parallel instructions. The assembler will put them in the proper containers. In the above example, the assembler will put the stw instruction in left container and the mulx instruction in the right container.
stw r2,@(r3,r4) ->
mulx a0,r8,r9
Two-line format. Execute the stw instruction followed by the mulx instruction sequentially. The first instruction goes in the left container and the second instruction goes into right container. The assembler will give an error if the machine ordering constraints are violated.
stw r2,@(r3,r4) <-
mulx a0,r8,r9
Same as previous example, except that the mulx instruction is executed before the stw instruction.

Since $ has no special meaning, you may use it in symbol names.

Node:D30V-Guarded, Next:, Previous:D30V-Chars, Up:D30V-Syntax

Guarded Execution

as supports the full range of guarded execution directives for each instruction. Just append the directive after the instruction proper. The directives are:

/tx
Execute the instruction if flag f0 is true.
/fx
Execute the instruction if flag f0 is false.
/xt
Execute the instruction if flag f1 is true.
/xf
Execute the instruction if flag f1 is false.
/tt
Execute the instruction if both flags f0 and f1 are true.
/tf
Execute the instruction if flag f0 is true and flag f1 is false.

Node:D30V-Regs, Next:, Previous:D30V-Guarded, Up:D30V-Syntax

Register Names

You can use the predefined symbols r0 through r63 to refer to the D30V registers. You can also use sp as an alias for r63 and link as an alias for r62. The accumulators are a0 and a1.

The D30V also has predefined symbols for these control registers and status bits:

psw
Processor Status Word
bpsw
Backup Processor Status Word
pc
Program Counter
bpc
Backup Program Counter
rpt_c
Repeat Count
rpt_s
Repeat Start address
rpt_e
Repeat End address
mod_s
Modulo Start address
mod_e
Modulo End address
iba
Instruction Break Address
f0
Flag 0
f1
Flag 1
f2
Flag 2
f3
Flag 3
f4
Flag 4
f5
Flag 5
f6
Flag 6
f7
Flag 7
s
Same as flag 4 (saturation flag)
v
Same as flag 5 (overflow flag)
va
Same as flag 6 (sticky overflow flag)
c
Same as flag 7 (carry/borrow flag)
b
Same as flag 7 (carry/borrow flag)

Node:D30V-Addressing, Previous:D30V-Regs, Up:D30V-Syntax

Addressing Modes

as understands the following addressing modes for the D30V. Rn in the following refers to any of the numbered registers, but not the control registers.

Rn
Register direct
@Rn
Register indirect
@Rn+
Register indirect with post-increment
@Rn-
Register indirect with post-decrement
@-SP
Register indirect with pre-decrement
@(disp, Rn)
Register indirect with displacement
addr
PC relative address (for branch or rep).
#imm
Immediate data (the # is optional and ignored)

Node:D30V-Float, Next:, Previous:D30V-Syntax, Up:D30V-Dependent

Floating Point

The D30V has no hardware floating point, but the .float and .double directives generates IEEE floating-point numbers for compatibility with other development tools.

Node:D30V-Opcodes, Previous:D30V-Float, Up:D30V-Dependent

Opcodes

For detailed information on the D30V machine instruction set, see D30V Architecture: A VLIW Microprocessor for Multimedia Applications (Mitsubishi Electric Corp.). as implements all the standard D30V opcodes. The only changes are those described in the section on size modifiers

Node:H8/300-Dependent, Next:, Previous:D30V-Dependent, Up:Machine Dependencies

H8/300 Dependent Features

Node:H8/300 Options, Next:, Up:H8/300-Dependent

Options

as has no additional command-line options for the Hitachi H8/300 family.

Node:H8/300 Syntax, Next:, Previous:H8/300 Options, Up:H8/300-Dependent

Syntax

Node:H8/300-Chars, Next:, Up:H8/300 Syntax

Special Characters

; is the line comment character.

$ can be used instead of a newline to separate statements. Therefore you may not use $ in symbol names on the H8/300.

Node:H8/300-Regs, Next:, Previous:H8/300-Chars, Up:H8/300 Syntax

Register Names

You can use predefined symbols of the form rnh and rnl to refer to the H8/300 registers as sixteen 8-bit general-purpose registers. n is a digit from 0 to 7); for instance, both r0h and r7l are valid register names.

You can also use the eight predefined symbols rn to refer to the H8/300 registers as 16-bit registers (you must use this form for addressing).

On the H8/300H, you can also use the eight predefined symbols ern (er0 ... er7) to refer to the 32-bit general purpose registers.

The two control registers are called pc (program counter; a 16-bit register, except on the H8/300H where it is 24 bits) and ccr (condition code register; an 8-bit register). r7 is used as the stack pointer, and can also be called sp.

Node:H8/300-Addressing, Previous:H8/300-Regs, Up:H8/300 Syntax

Addressing Modes

as understands the following addressing modes for the H8/300:
rn
Register direct
@rn
Register indirect
@(d, rn)
@(d:16, rn)
@(d:24, rn)
Register indirect: 16-bit or 24-bit displacement d from register n. (24-bit displacements are only meaningful on the H8/300H.)
@rn+
Register indirect with post-increment
@-rn
Register indirect with pre-decrement
@aa
@aa:8
@aa:16
@aa:24
Absolute address aa. (The address size :24 only makes sense on the H8/300H.)
#xx
#xx:8
#xx:16
#xx:32
Immediate data xx. You may specify the :8, :16, or :32 for clarity, if you wish; but as neither requires this nor uses it--the data size required is taken from context.
@@aa
@@aa:8
Memory indirect. You may specify the :8 for clarity, if you wish; but as neither requires this nor uses it.

Node:H8/300 Floating Point, Next:, Previous:H8/300 Syntax, Up:H8/300-Dependent

Floating Point

The H8/300 family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.

Node:H8/300 Directives, Next:, Previous:H8/300 Floating Point, Up:H8/300-Dependent

H8/300 Machine Directives

as has only one machine-dependent directive for the H8/300:

.h8300h
Recognize and emit additional instructions for the H8/300H variant, and also make .int emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

On the H8/300 family (including the H8/300H) .word directives generate 16-bit numbers.

Node:H8/300 Opcodes, Previous:H8/300 Directives, Up:H8/300-Dependent

Opcodes

For detailed information on the H8/300 machine instruction set, see H8/300 Series Programming Manual (Hitachi ADE-602-025). For information specific to the H8/300H, see H8/300H Series Programming Manual (Hitachi).

as implements all the standard H8/300 opcodes. No additional pseudo-instructions are needed on this family.

The following table summarizes the H8/300 opcodes, and their arguments. Entries marked * are opcodes used only on the H8/300H. 

         Legend:
            Rs   source register
            Rd   destination register
            abs  absolute address
            imm  immediate data
         disp:N  N-bit displacement from a register
        pcrel:N  N-bit displacement relative to program counter

   add.b #imm,rd              *  andc #imm,ccr
   add.b rs,rd                   band #imm,rd
   add.w rs,rd                   band #imm,@rd
*  add.w #imm,rd                 band #imm,@abs:8
*  add.l rs,rd                   bra  pcrel:8
*  add.l #imm,rd              *  bra  pcrel:16
   adds #imm,rd                  bt   pcrel:8
   addx #imm,rd               *  bt   pcrel:16
   addx rs,rd                    brn  pcrel:8
   and.b #imm,rd              *  brn  pcrel:16
   and.b rs,rd                   bf   pcrel:8
*  and.w rs,rd                *  bf   pcrel:16
*  and.w #imm,rd                 bhi  pcrel:8
*  and.l #imm,rd              *  bhi  pcrel:16
*  and.l rs,rd                   bls  pcrel:8

*  bls  pcrel:16                 bld  #imm,rd
   bcc  pcrel:8                  bld  #imm,@rd
*  bcc  pcrel:16                 bld  #imm,@abs:8
   bhs  pcrel:8                  bnot #imm,rd
*  bhs  pcrel:16                 bnot #imm,@rd
   bcs  pcrel:8                  bnot #imm,@abs:8
*  bcs  pcrel:16                 bnot rs,rd
   blo  pcrel:8                  bnot rs,@rd
*  blo  pcrel:16                 bnot rs,@abs:8
   bne  pcrel:8                  bor  #imm,rd
*  bne  pcrel:16                 bor  #imm,@rd
   beq  pcrel:8                  bor  #imm,@abs:8
*  beq  pcrel:16                 bset #imm,rd
   bvc  pcrel:8                  bset #imm,@rd
*  bvc  pcrel:16                 bset #imm,@abs:8
   bvs  pcrel:8                  bset rs,rd
*  bvs  pcrel:16                 bset rs,@rd
   bpl  pcrel:8                  bset rs,@abs:8
*  bpl  pcrel:16                 bsr  pcrel:8
   bmi  pcrel:8                  bsr  pcrel:16
*  bmi  pcrel:16                 bst  #imm,rd
   bge  pcrel:8                  bst  #imm,@rd
*  bge  pcrel:16                 bst  #imm,@abs:8
   blt  pcrel:8                  btst #imm,rd
*  blt  pcrel:16                 btst #imm,@rd
   bgt  pcrel:8                  btst #imm,@abs:8
*  bgt  pcrel:16                 btst rs,rd
   ble  pcrel:8                  btst rs,@rd
*  ble  pcrel:16                 btst rs,@abs:8
   bclr #imm,rd                  bxor #imm,rd
   bclr #imm,@rd                 bxor #imm,@rd
   bclr #imm,@abs:8              bxor #imm,@abs:8
   bclr rs,rd                    cmp.b #imm,rd
   bclr rs,@rd                   cmp.b rs,rd
   bclr rs,@abs:8                cmp.w rs,rd
   biand #imm,rd                 cmp.w rs,rd
   biand #imm,@rd             *  cmp.w #imm,rd
   biand #imm,@abs:8          *  cmp.l #imm,rd
   bild #imm,rd               *  cmp.l rs,rd
   bild #imm,@rd                 daa  rs
   bild #imm,@abs:8              das  rs
   bior #imm,rd                  dec.b rs
   bior #imm,@rd              *  dec.w #imm,rd
   bior #imm,@abs:8           *  dec.l #imm,rd
   bist #imm,rd                  divxu.b rs,rd
   bist #imm,@rd              *  divxu.w rs,rd
   bist #imm,@abs:8           *  divxs.b rs,rd
   bixor #imm,rd              *  divxs.w rs,rd
   bixor #imm,@rd                eepmov
   bixor #imm,@abs:8          *  eepmovw

*  exts.w rd                     mov.w rs,@abs:16
*  exts.l rd                  *  mov.l #imm,rd
*  extu.w rd                  *  mov.l rs,rd
*  extu.l rd                  *  mov.l @rs,rd
   inc  rs                    *  mov.l @(disp:16,rs),rd
*  inc.w #imm,rd              *  mov.l @(disp:24,rs),rd
*  inc.l #imm,rd              *  mov.l @rs+,rd
   jmp  @rs                   *  mov.l @abs:16,rd
   jmp  abs                   *  mov.l @abs:24,rd
   jmp  @@abs:8               *  mov.l rs,@rd
   jsr  @rs                   *  mov.l rs,@(disp:16,rd)
   jsr  abs                   *  mov.l rs,@(disp:24,rd)
   jsr  @@abs:8               *  mov.l rs,@-rd
   ldc  #imm,ccr              *  mov.l rs,@abs:16
   ldc  rs,ccr                *  mov.l rs,@abs:24
*  ldc  @abs:16,ccr              movfpe @abs:16,rd
*  ldc  @abs:24,ccr              movtpe rs,@abs:16
*  ldc  @(disp:16,rs),ccr        mulxu.b rs,rd
*  ldc  @(disp:24,rs),ccr     *  mulxu.w rs,rd
*  ldc  @rs+,ccr              *  mulxs.b rs,rd
*  ldc  @rs,ccr               *  mulxs.w rs,rd
*  mov.b @(disp:24,rs),rd        neg.b rs
*  mov.b rs,@(disp:24,rd)     *  neg.w rs
   mov.b @abs:16,rd           *  neg.l rs
   mov.b rs,rd                   nop
   mov.b @abs:8,rd               not.b rs
   mov.b rs,@abs:8            *  not.w rs
   mov.b rs,rd                *  not.l rs
   mov.b #imm,rd                 or.b #imm,rd
   mov.b @rs,rd                  or.b rs,rd
   mov.b @(disp:16,rs),rd     *  or.w #imm,rd
   mov.b @rs+,rd              *  or.w rs,rd
   mov.b @abs:8,rd            *  or.l #imm,rd
   mov.b rs,@rd               *  or.l rs,rd
   mov.b rs,@(disp:16,rd)        orc  #imm,ccr
   mov.b rs,@-rd                 pop.w rs
   mov.b rs,@abs:8            *  pop.l rs
   mov.w rs,@rd                  push.w rs
*  mov.w @(disp:24,rs),rd     *  push.l rs
*  mov.w rs,@(disp:24,rd)        rotl.b rs
*  mov.w @abs:24,rd           *  rotl.w rs
*  mov.w rs,@abs:24           *  rotl.l rs
   mov.w rs,rd                   rotr.b rs
   mov.w #imm,rd              *  rotr.w rs
   mov.w @rs,rd               *  rotr.l rs
   mov.w @(disp:16,rs),rd        rotxl.b rs
   mov.w @rs+,rd              *  rotxl.w rs
   mov.w @abs:16,rd           *  rotxl.l rs
   mov.w rs,@(disp:16,rd)        rotxr.b rs
   mov.w rs,@-rd              *  rotxr.w rs

*  rotxr.l rs                 *  stc  ccr,@(disp:24,rd)
   bpt                        *  stc  ccr,@-rd
   rte                        *  stc  ccr,@abs:16
   rts                        *  stc  ccr,@abs:24
   shal.b rs                     sub.b rs,rd
*  shal.w rs                     sub.w rs,rd
*  shal.l rs                  *  sub.w #imm,rd
   shar.b rs                  *  sub.l rs,rd
*  shar.w rs                  *  sub.l #imm,rd
*  shar.l rs                     subs #imm,rd
   shll.b rs                     subx #imm,rd
*  shll.w rs                     subx rs,rd
*  shll.l rs                  *  trapa #imm
   shlr.b rs                     xor  #imm,rd
*  shlr.w rs                     xor  rs,rd
*  shlr.l rs                  *  xor.w #imm,rd
   sleep                      *  xor.w rs,rd
   stc  ccr,rd                *  xor.l #imm,rd
*  stc  ccr,@rs               *  xor.l rs,rd
*  stc  ccr,@(disp:16,rd)        xorc #imm,ccr

Four H8/300 instructions (add, cmp, mov, sub) are defined with variants using the suffixes .b, .w, and .l to specify the size of a memory operand. as supports these suffixes, but does not require them; since one of the operands is always a register, as can deduce the correct size.

For example, since r0 refers to a 16-bit register, 

mov    r0,@foo

is equivalent to

mov.w  r0,@foo

If you use the size suffixes, as issues a warning when the suffix and the register size do not match.

Node:H8/500-Dependent, Next:, Previous:H8/300-Dependent, Up:Machine Dependencies

H8/500 Dependent Features

Node:H8/500 Options, Next:, Up:H8/500-Dependent

Options

as has no additional command-line options for the Hitachi H8/500 family.

Node:H8/500 Syntax, Next:, Previous:H8/500 Options, Up:H8/500-Dependent

Syntax

Node:H8/500-Chars, Next:, Up:H8/500 Syntax

Special Characters

! is the line comment character.

; can be used instead of a newline to separate statements.

Since $ has no special meaning, you may use it in symbol names.

Node:H8/500-Regs, Next:, Previous:H8/500-Chars, Up:H8/500 Syntax

Register Names

You can use the predefined symbols r0, r1, r2, r3, r4, r5, r6, and r7 to refer to the H8/500 registers.

The H8/500 also has these control registers:

cp
code pointer
dp
data pointer
bp
base pointer
tp
stack top pointer
ep
extra pointer
sr
status register
ccr
condition code register

All registers are 16 bits long. To represent 32 bit numbers, use two adjacent registers; for distant memory addresses, use one of the segment pointers (cp for the program counter; dp for r0-r3; ep for r4 and r5; and tp for r6 and r7.

Node:H8/500-Addressing, Previous:H8/500-Regs, Up:H8/500 Syntax

Addressing Modes

as understands the following addressing modes for the H8/500:
Rn
Register direct
@Rn
Register indirect
@(d:8, Rn)
Register indirect with 8 bit signed displacement
@(d:16, Rn)
Register indirect with 16 bit signed displacement
@-Rn
Register indirect with pre-decrement
@Rn+
Register indirect with post-increment
@aa:8
8 bit absolute address
@aa:16
16 bit absolute address
#xx:8
8 bit immediate
#xx:16
16 bit immediate

Node:H8/500 Floating Point, Next:, Previous:H8/500 Syntax, Up:H8/500-Dependent

Floating Point

The H8/500 family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.

Node:H8/500 Directives, Next:, Previous:H8/500 Floating Point, Up:H8/500-Dependent

H8/500 Machine Directives

as has no machine-dependent directives for the H8/500. However, on this platform the .int and .word directives generate 16-bit numbers.

Node:H8/500 Opcodes, Previous:H8/500 Directives, Up:H8/500-Dependent

Opcodes

For detailed information on the H8/500 machine instruction set, see H8/500 Series Programming Manual (Hitachi M21T001).

as implements all the standard H8/500 opcodes. No additional pseudo-instructions are needed on this family.

The following table summarizes H8/500 opcodes and their operands: 

Legend:
abs8      8-bit absolute address
abs16     16-bit absolute address
abs24     24-bit absolute address
crb       ccr, br, ep, dp, tp, dp
disp8     8-bit displacement
ea        rn, @rn, @(d:8, rn), @(d:16, rn),
          @-rn, @rn+, @aa:8, @aa:16,
          #xx:8, #xx:16
ea_mem    @rn, @(d:8, rn), @(d:16, rn),
          @-rn, @rn+, @aa:8, @aa:16
ea_noimm  rn, @rn, @(d:8, rn), @(d:16, rn),
          @-rn, @rn+, @aa:8, @aa:16
fp        r6
imm4      4-bit immediate data
imm8      8-bit immediate data
imm16     16-bit immediate data
pcrel8    8-bit offset from program counter
pcrel16   16-bit offset from program counter
qim       -2, -1, 1, 2
rd        any register
rs        a register distinct from rd
rlist     comma-separated list of registers in parentheses;
          register ranges rd-rs are allowed
sp        stack pointer (r7)
sr        status register
sz        size; .b or .w.  If omitted, default .w

ldc[.b] ea,crb                 bcc[.w] pcrel16
ldc[.w] ea,sr                  bcc[.b] pcrel8
add[:q] sz qim,ea_noimm        bhs[.w] pcrel16
add[:g] sz ea,rd               bhs[.b] pcrel8
adds sz ea,rd                  bcs[.w] pcrel16
addx sz ea,rd                  bcs[.b] pcrel8
and sz ea,rd                   blo[.w] pcrel16
andc[.b] imm8,crb              blo[.b] pcrel8
andc[.w] imm16,sr              bne[.w] pcrel16
bpt                            bne[.b] pcrel8
bra[.w] pcrel16                beq[.w] pcrel16
bra[.b] pcrel8                 beq[.b] pcrel8
bt[.w] pcrel16                 bvc[.w] pcrel16
bt[.b] pcrel8                  bvc[.b] pcrel8
brn[.w] pcrel16                bvs[.w] pcrel16
brn[.b] pcrel8                 bvs[.b] pcrel8
bf[.w] pcrel16                 bpl[.w] pcrel16
bf[.b] pcrel8                  bpl[.b] pcrel8
bhi[.w] pcrel16                bmi[.w] pcrel16
bhi[.b] pcrel8                 bmi[.b] pcrel8
bls[.w] pcrel16                bge[.w] pcrel16
bls[.b] pcrel8                 bge[.b] pcrel8

blt[.w] pcrel16                mov[:g][.b] imm8,ea_mem
blt[.b] pcrel8                 mov[:g][.w] imm16,ea_mem
bgt[.w] pcrel16                movfpe[.b] ea,rd
bgt[.b] pcrel8                 movtpe[.b] rs,ea_noimm
ble[.w] pcrel16                mulxu sz ea,rd
ble[.b] pcrel8                 neg sz ea
bclr sz imm4,ea_noimm          nop
bclr sz rs,ea_noimm            not sz ea
bnot sz imm4,ea_noimm          or sz ea,rd
bnot sz rs,ea_noimm            orc[.b] imm8,crb
bset sz imm4,ea_noimm          orc[.w] imm16,sr
bset sz rs,ea_noimm            pjmp abs24
bsr[.b] pcrel8                 pjmp @rd
bsr[.w] pcrel16                pjsr abs24
btst sz imm4,ea_noimm          pjsr @rd
btst sz rs,ea_noimm            prtd imm8
clr sz ea                      prtd imm16
cmp[:e][.b] imm8,rd            prts
cmp[:i][.w] imm16,rd           rotl sz ea
cmp[:g].b imm8,ea_noimm        rotr sz ea
cmp[:g][.w] imm16,ea_noimm     rotxl sz ea
Cmp[:g] sz ea,rd               rotxr sz ea
dadd rs,rd                     rtd imm8
divxu sz ea,rd                 rtd imm16
dsub rs,rd                     rts
exts[.b] rd                    scb/f rs,pcrel8
extu[.b] rd                    scb/ne rs,pcrel8
jmp @rd                        scb/eq rs,pcrel8
jmp @(imm8,rd)                 shal sz ea
jmp @(imm16,rd)                shar sz ea
jmp abs16                      shll sz ea
jsr @rd                        shlr sz ea
jsr @(imm8,rd)                 sleep
jsr @(imm16,rd)                stc[.b] crb,ea_noimm
jsr abs16                      stc[.w] sr,ea_noimm
ldm @sp+,(rlist)               stm (rlist),@-sp
link fp,imm8                   sub sz ea,rd
link fp,imm16                  subs sz ea,rd
mov[:e][.b] imm8,rd            subx sz ea,rd
mov[:i][.w] imm16,rd           swap[.b] rd
mov[:l][.w] abs8,rd            tas[.b] ea
mov[:l].b abs8,rd              trapa imm4
mov[:s][.w] rs,abs8            trap/vs
mov[:s].b rs,abs8              tst sz ea
mov[:f][.w] @(disp8,fp),rd     unlk fp
mov[:f][.w] rs,@(disp8,fp)     xch[.w] rs,rd
mov[:f].b @(disp8,fp),rd       xor sz ea,rd
mov[:f].b rs,@(disp8,fp)       xorc.b imm8,crb
mov[:g] sz rs,ea_mem           xorc.w imm16,sr
mov[:g] sz ea,rd

Node:HPPA-Dependent, Next:, Previous:H8/500-Dependent, Up:Machine Dependencies

HPPA Dependent Features

Node:HPPA Notes, Next:, Up:HPPA-Dependent

Notes

As a back end for GNU CC as has been throughly tested and should work extremely well. We have tested it only minimally on hand written assembly code and no one has tested it much on the assembly output from the HP compilers.

The format of the debugging sections has changed since the original as port (version 1.3X) was released; therefore, you must rebuild all HPPA objects and libraries with the new assembler so that you can debug the final executable.

The HPPA as port generates a small subset of the relocations available in the SOM and ELF object file formats. Additional relocation support will be added as it becomes necessary.

Node:HPPA Options, Next:, Previous:HPPA Notes, Up:HPPA-Dependent

Options

as has no machine-dependent command-line options for the HPPA.

Node:HPPA Syntax, Next:, Previous:HPPA Options, Up:HPPA-Dependent

Syntax

The assembler syntax closely follows the HPPA instruction set reference manual; assembler directives and general syntax closely follow the HPPA assembly language reference manual, with a few noteworthy differences.

First, a colon may immediately follow a label definition. This is simply for compatibility with how most assembly language programmers write code.

Some obscure expression parsing problems may affect hand written code which uses the spop instructions, or code which makes significant use of the ! line separator.

as is much less forgiving about missing arguments and other similar oversights than the HP assembler. as notifies you of missing arguments as syntax errors; this is regarded as a feature, not a bug.

Finally, as allows you to use an external symbol without explicitly importing the symbol. Warning: in the future this will be an error for HPPA targets.

Special characters for HPPA targets include:

; is the line comment character.

! can be used instead of a newline to separate statements.

Since $ has no special meaning, you may use it in symbol names.

Node:HPPA Floating Point, Next:, Previous:HPPA Syntax, Up:HPPA-Dependent

Floating Point

The HPPA family uses IEEE floating-point numbers.

Node:HPPA Directives, Next:, Previous:HPPA Floating Point, Up:HPPA-Dependent

HPPA Assembler Directives

as for the HPPA supports many additional directives for compatibility with the native assembler. This section describes them only briefly. For detailed information on HPPA-specific assembler directives, see HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001).

as does not support the following assembler directives described in the HP manual: 

.endm           .liston
.enter          .locct
.leave          .macro
.listoff

Beyond those implemented for compatibility, as supports one additional assembler directive for the HPPA: .param. It conveys register argument locations for static functions. Its syntax closely follows the .export directive.

These are the additional directives in as for the HPPA:

.block n
.blockz n
Reserve n bytes of storage, and initialize them to zero.
.call
Mark the beginning of a procedure call. Only the special case with no arguments is allowed.
.callinfo [ param=value, ... ] [ flag, ... ]
Specify a number of parameters and flags that define the environment for a procedure.

param may be any of frame (frame size), entry_gr (end of general register range), entry_fr (end of float register range), entry_sr (end of space register range).

The values for flag are calls or caller (proc has subroutines), no_calls (proc does not call subroutines), save_rp (preserve return pointer), save_sp (proc preserves stack pointer), no_unwind (do not unwind this proc), hpux_int (proc is interrupt routine).

.code
Assemble into the standard section called $TEXT$, subsection $CODE$.
.copyright "string"
In the SOM object format, insert string into the object code, marked as a copyright string.
.copyright "string"
In the ELF object format, insert string into the object code, marked as a version string.
.enter
Not yet supported; the assembler rejects programs containing this directive.
.entry
Mark the beginning of a procedure.
.exit
Mark the end of a procedure.
.export name [ ,typ ] [ ,param=r ]
Make a procedure name available to callers. typ, if present, must be one of absolute, code (ELF only, not SOM), data, entry, data, entry, millicode, plabel, pri_prog, or sec_prog.

param, if present, provides either relocation information for the procedure arguments and result, or a privilege level. param may be argwn (where n ranges from 0 to 3, and indicates one of four one-word arguments); rtnval (the procedure's result); or priv_lev (privilege level). For arguments or the result, r specifies how to relocate, and must be one of no (not relocatable), gr (argument is in general register), fr (in floating point register), or fu (upper half of float register). For priv_lev, r is an integer.

.half n
Define a two-byte integer constant n; synonym for the portable as directive .short.
.import name [ ,typ ]
Converse of .export; make a procedure available to call. The arguments use the same conventions as the first two arguments for .export.
.label name
Define name as a label for the current assembly location.
.leave
Not yet supported; the assembler rejects programs containing this directive.
.origin lc
Advance location counter to lc. Synonym for the {No value for `as'} portable directive .org.
.param name [ ,typ ] [ ,param=r ]
Similar to .export, but used for static procedures.
.proc
Use preceding the first statement of a procedure.
.procend
Use following the last statement of a procedure.
label .reg expr
Synonym for .equ; define label with the absolute expression expr as its value.
.space secname [ ,params ]
Switch to section secname, creating a new section by that name if necessary. You may only use params when creating a new section, not when switching to an existing one. secname may identify a section by number rather than by name.

If specified, the list params declares attributes of the section, identified by keywords. The keywords recognized are spnum=exp (identify this section by the number exp, an absolute expression), sort=exp (order sections according to this sort key when linking; exp is an absolute expression), unloadable (section contains no loadable data), notdefined (this section defined elsewhere), and private (data in this section not available to other programs).

.spnum secnam
Allocate four bytes of storage, and initialize them with the section number of the section named secnam. (You can define the section number with the HPPA .space directive.)
.string "str"
Copy the characters in the string str to the object file. See Strings, for information on escape sequences you can use in as strings.

Warning! The HPPA version of .string differs from the usual as definition: it does not write a zero byte after copying str.

.stringz "str"
Like .string, but appends a zero byte after copying str to object file.
.subspa name [ ,params ]
.nsubspa name [ ,params ]
Similar to .space, but selects a subsection name within the current section. You may only specify params when you create a subsection (in the first instance of .subspa for this name).

If specified, the list params declares attributes of the subsection, identified by keywords. The keywords recognized are quad=expr ("quadrant" for this subsection), align=expr (alignment for beginning of this subsection; a power of two), access=expr (value for "access rights" field), sort=expr (sorting order for this subspace in link), code_only (subsection contains only code), unloadable (subsection cannot be loaded into memory), common (subsection is common block), dup_comm (initialized data may have duplicate names), or zero (subsection is all zeros, do not write in object file).

.nsubspa always creates a new subspace with the given name, even if one with the same name already exists.

.version "str"
Write str as version identifier in object code.

Node:HPPA Opcodes, Previous:HPPA Directives, Up:HPPA-Dependent

Opcodes

For detailed information on the HPPA machine instruction set, see PA-RISC Architecture and Instruction Set Reference Manual (HP 09740-90039).

Node:ESA/390-Dependent, Next:, Previous:HPPA-Dependent, Up:Machine Dependencies

ESA/390 Dependent Features

Node:ESA/390 Notes, Next:, Up:ESA/390-Dependent

Notes

The ESA/390 as port is currently intended to be a back-end for the GNU CC compiler. It is not HLASM compatible, although it does support a subset of some of the HLASM directives. The only supported binary file format is ELF; none of the usual MVS/VM/OE/USS object file formats, such as ESD or XSD, are supported.

When used with the GNU CC compiler, the ESA/390 as will produce correct, fully relocated, functional binaries, and has been used to compile and execute large projects. However, many aspects should still be considered experimental; these include shared library support, dynamically loadable objects, and any relocation other than the 31-bit relocation.

Node:ESA/390 Options, Next:, Previous:ESA/390 Notes, Up:ESA/390-Dependent

Options

as has no machine-dependent command-line options for the ESA/390.

Node:ESA/390 Syntax, Next:, Previous:ESA/390 Options, Up:ESA/390-Dependent

Syntax

The opcode/operand syntax follows the ESA/390 Principles of Operation manual; assembler directives and general syntax are loosely based on the prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives are not supported for the most part, with the exception of those described herein.

A leading dot in front of directives is optional, and the case of directives is ignored; thus for example, .using and USING have the same effect.

A colon may immediately follow a label definition. This is simply for compatibility with how most assembly language programmers write code.

# is the line comment character.

; can be used instead of a newline to separate statements.

Since $ has no special meaning, you may use it in symbol names.

Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, fp6. By using thesse symbolic names, as can detect simple syntax errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base for r3 and rpgt or r.pgt for r4.

* is the current location counter. Unlike . it is always relative to the last USING directive. Note that this means that expressions cannot use multiplication, as any occurence of * will be interpreted as a location counter.

All labels are relative to the last USING. Thus, branches to a label always imply the use of base+displacement.

Many of the usual forms of address constants / address literals are supported. Thus, 

	.using	*,r3
	L	r15,=A(some_routine)
	LM	r6,r7,=V(some_longlong_extern)
	A	r1,=F'12'
	AH	r0,=H'42'
	ME	r6,=E'3.1416'
	MD	r6,=D'3.14159265358979'
	O	r6,=XL4'cacad0d0'
	.ltorg
should all behave as expected: that is, an entry in the literal pool will be created (or reused if it already exists), and the instruction operands will be the displacement into the literal pool using the current base register (as last declared with the .using directive).

Node:ESA/390 Floating Point, Next:, Previous:ESA/390 Syntax, Up:ESA/390-Dependent

Floating Point

The assembler generates only IEEE floating-point numbers. The older floiating point formats are not supported.

Node:ESA/390 Directives, Next:, Previous:ESA/390 Floating Point, Up:ESA/390-Dependent

ESA/390 Assembler Directives

as for the ESA/390 supports all of the standard ELF/SVR4 assembler directives that are documented in the main part of this documentation. Several additional directives are supported in order to implement the ESA/390 addressing model. The most important of these are .using and .ltorg

These are the additional directives in as for the ESA/390:

.dc
A small subset of the usual DC directive is supported.
.drop regno
Stop using regno as the base register. The regno must have been previously declared with a .using directive in the same section as the current section.
.ebcdic string
Emit the EBCDIC equivalent of the indicated string. The emitted string will be null terminated. Note that the directives .string etc. emit ascii strings by default.
EQU
The standard HLASM-style EQU directive is not supported; however, the standard as directive .equ can be used to the same effect.
.ltorg
Dump the literal pool accumulated so far; begin a new literal pool. The literal pool will be written in the current section; in order to generate correct assembly, a .using must have been previously specified in the same section.
.using expr,regno
Use regno as the base register for all subsequent RX, RS, and SS form instructions. The expr will be evaluated to obtain the base address; usually, expr will merely be *.

This assembler allows two .using directives to be simultaneously outstanding, one in the .text section, and one in another section (typically, the .data section). This feature allows dynamically loaded objects to be implemented in a relatively straightforward way. A .using directive must always be specified in the .text section; this will specify the base register that will be used for branches in the .text section. A second .using may be specified in another section; this will specify the base register that is used for non-label address literals. When a second .using is specified, then the subsequent .ltorg must be put in the same section; otherwise an error will result.

Thus, for example, the following code uses r3 to address branch targets and r4 to address the literal pool, which has been written to the .data section. The is, the constants =A(some_routine), =H'42' and =E'3.1416' will all appear in the .data section. 

.data
	.using  LITPOOL,r4
.text
	BASR	r3,0
	.using	*,r3
        B       START
	.long	LITPOOL
START:
	L	r4,4(,r3)
	L	r15,=A(some_routine)
	LTR	r15,r15
	BNE	LABEL
	AH	r0,=H'42'
LABEL:
	ME	r6,=E'3.1416'
.data
LITPOOL:
	.ltorg

Note that this dual-.using directive semantics extends and is not compatible with HLASM semantics. Note that this assembler directive does not support the full range of HLASM semantics.

Node:ESA/390 Opcodes, Previous:ESA/390 Directives, Up:ESA/390-Dependent

Opcodes

For detailed information on the ESA/390 machine instruction set, see ESA/390 Principles of Operation (IBM Publication Number DZ9AR004).

Node:i386-Dependent, Next:, Previous:ESA/390-Dependent, Up:Machine Dependencies

80386 Dependent Features

The i386 version as supports both the original Intel 386 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture extending the Intel architecture to 64-bits.

Node:i386-Options, Next:, Up:i386-Dependent

Options

The i386 version of as has a few machine dependent options:

--32 | --64
Select the word size, either 32 bits or 64 bits. Selecting 32-bit implies Intel i386 architecture, while 64-bit implies AMD x86-64 architecture.

These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 32-bit platform you have to add -enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform).

Node:i386-Syntax, Next:, Previous:i386-Options, Up:i386-Dependent

AT&T Syntax versus Intel Syntax

as now supports assembly using Intel assembler syntax. .intel_syntax selects Intel mode, and .att_syntax switches back to the usual AT&T mode for compatibility with the output of gcc. Either of these directives may have an optional argument, prefix, or noprefix specifying whether registers require a % prefix. AT&T System V/386 assembler syntax is quite different from Intel syntax. We mention these differences because almost all 80386 documents use Intel syntax. Notable differences between the two syntaxes are:

Node:i386-Mnemonics, Next:, Previous:i386-Syntax, Up:i386-Dependent

Instruction Naming

Instruction mnemonics are suffixed with one character modifiers which specify the size of operands. The letters b, w, l and q specify byte, word, long and quadruple word operands. If no suffix is specified by an instruction then as tries to fill in the missing suffix based on the destination register operand (the last one by convention). Thus, mov %ax, %bx is equivalent to movw %ax, %bx; also, mov $1, %bx is equivalent to movw $1, bx. Note that this is incompatible with the AT&T Unix assembler which assumes that a missing mnemonic suffix implies long operand size. (This incompatibility does not affect compiler output since compilers always explicitly specify the mnemonic suffix.)

Almost all instructions have the same names in AT&T and Intel format. There are a few exceptions. The sign extend and zero extend instructions need two sizes to specify them. They need a size to sign/zero extend from and a size to zero extend to. This is accomplished by using two instruction mnemonic suffixes in AT&T syntax. Base names for sign extend and zero extend are movs... and movz... in AT&T syntax (movsx and movzx in Intel syntax). The instruction mnemonic suffixes are tacked on to this base name, the from suffix before the to suffix. Thus, movsbl %al, %edx is AT&T syntax for "move sign extend from %al to %edx." Possible suffixes, thus, are bl (from byte to long), bw (from byte to word), wl (from word to long), bq (from byte to quadruple word), wq (from word to quadruple word), and lq (from long to quadruple word).

The Intel-syntax conversion instructions

are called cbtw, cwtl, cwtd, cltd, cltq, and cqto in AT&T naming. as accepts either naming for these instructions.

Far call/jump instructions are lcall and ljmp in AT&T syntax, but are call far and jump far in Intel convention.

Node:i386-Regs, Next:, Previous:i386-Mnemonics, Up:i386-Dependent

Register Naming

Register operands are always prefixed with %. The 80386 registers consist of

The AMD x86-64 architecture extends the register set by:

Node:i386-Prefixes, Next:, Previous:i386-Regs, Up:i386-Dependent

Instruction Prefixes

Instruction prefixes are used to modify the following instruction. They are used to repeat string instructions, to provide section overrides, to perform bus lock operations, and to change operand and address sizes. (Most instructions that normally operate on 32-bit operands will use 16-bit operands if the instruction has an "operand size" prefix.) Instruction prefixes are best written on the same line as the instruction they act upon. For example, the scas (scan string) instruction is repeated with: 

        repne scas %es:(%edi),%al

You may also place prefixes on the lines immediately preceding the instruction, but this circumvents checks that as does with prefixes, and will not work with all prefixes.

Here is a list of instruction prefixes:

Node:i386-Memory, Next:, Previous:i386-Prefixes, Up:i386-Dependent

Memory References

An Intel syntax indirect memory reference of the form 

section:[base + index*scale + disp]

is translated into the AT&T syntax 

section:disp(base, index, scale)

where base and index are the optional 32-bit base and index registers, disp is the optional displacement, and scale, taking the values 1, 2, 4, and 8, multiplies index to calculate the address of the operand. If no scale is specified, scale is taken to be 1. section specifies the optional section register for the memory operand, and may override the default section register (see a 80386 manual for section register defaults). Note that section overrides in AT&T syntax must be preceded by a %. If you specify a section override which coincides with the default section register, as does not output any section register override prefixes to assemble the given instruction. Thus, section overrides can be specified to emphasize which section register is used for a given memory operand.

Here are some examples of Intel and AT&T style memory references:

AT&T: -4(%ebp), Intel: [ebp - 4]
base is %ebp; disp is -4. section is missing, and the default section is used (%ss for addressing with %ebp as the base register). index, scale are both missing.
AT&T: foo(,%eax,4), Intel: [foo + eax*4]
index is %eax (scaled by a scale 4); disp is foo. All other fields are missing. The section register here defaults to %ds.
AT&T: foo(,1); Intel [foo]
This uses the value pointed to by foo as a memory operand. Note that base and index are both missing, but there is only one ,. This is a syntactic exception.
AT&T: %gs:foo; Intel gs:foo
This selects the contents of the variable foo with section register section being %gs.

Absolute (as opposed to PC relative) call and jump operands must be prefixed with *. If no * is specified, as always chooses PC relative addressing for jump/call labels.

Any instruction that has a memory operand, but no register operand, must specify its size (byte, word, long, or quadruple) with an instruction mnemonic suffix (b, w, l or q, respectively).

The x86-64 architecture adds an RIP (instruction pointer relative) addressing. This addressing mode is specified by using rip as a base register. Only constant offsets are valid. For example:

AT&T: 1234(%rip), Intel: [rip + 1234]
Points to the address 1234 bytes past the end of the current instruction.
AT&T: symbol(%rip), Intel: [rip + symbol]
Points to the symbol in RIP relative way, this is shorter than the default absolute addressing.

Other addressing modes remain unchanged in x86-64 architecture, except registers used are 64-bit instead of 32-bit.

Node:i386-Jumps, Next:, Previous:i386-Memory, Up:i386-Dependent

Handling of Jump Instructions

Jump instructions are always optimized to use the smallest possible displacements. This is accomplished by using byte (8-bit) displacement jumps whenever the target is sufficiently close. If a byte displacement is insufficient a long displacement is used. We do not support word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump instruction with the data16 instruction prefix), since the 80386 insists upon masking %eip to 16 bits after the word displacement is added. (See also see i386-Arch)

Note that the jcxz, jecxz, loop, loopz, loope, loopnz and loopne instructions only come in byte displacements, so that if you use these instructions (gcc does not use them) you may get an error message (and incorrect code). The AT&T 80386 assembler tries to get around this problem by expanding jcxz foo to 

         jcxz cx_zero
         jmp cx_nonzero
cx_zero: jmp foo
cx_nonzero:

Node:i386-Float, Next:, Previous:i386-Jumps, Up:i386-Dependent

Floating Point

All 80387 floating point types except packed BCD are supported. (BCD support may be added without much difficulty). These data types are 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), and extended (80-bit) precision floating point. Each supported type has an instruction mnemonic suffix and a constructor associated with it. Instruction mnemonic suffixes specify the operand's data type. Constructors build these data types into memory.

Register to register operations should not use instruction mnemonic suffixes. fstl %st, %st(1) will give a warning, and be assembled as if you wrote fst %st, %st(1), since all register to register operations use 80-bit floating point operands. (Contrast this with fstl %st, mem, which converts %st from 80-bit to 64-bit floating point format, then stores the result in the 4 byte location mem)

Node:i386-SIMD, Next:, Previous:i386-Float, Up:i386-Dependent

Intel's MMX and AMD's 3DNow! SIMD Operations

as supports Intel's MMX instruction set (SIMD instructions for integer data), available on Intel's Pentium MMX processors and Pentium II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow! instruction set (SIMD instructions for 32-bit floating point data) available on AMD's K6-2 processor and possibly others in the future.

Currently, as does not support Intel's floating point SIMD, Katmai (KNI).

The eight 64-bit MMX operands, also used by 3DNow!, are called %mm0, %mm1, ... %mm7. They contain eight 8-bit integers, four 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit floating point values. The MMX registers cannot be used at the same time as the floating point stack.

See Intel and AMD documentation, keeping in mind that the operand order in instructions is reversed from the Intel syntax.

Node:i386-16bit, Next:, Previous:i386-SIMD, Up:i386-Dependent

Writing 16-bit Code

While as normally writes only "pure" 32-bit i386 code or 64-bit x86-64 code depending on the default configuration, it also supports writing code to run in real mode or in 16-bit protected mode code segments. To do this, put a .code16 or .code16gcc directive before the assembly language instructions to be run in 16-bit mode. You can switch as back to writing normal 32-bit code with the .code32 directive.

.code16gcc provides experimental support for generating 16-bit code from gcc, and differs from .code16 in that call, ret, enter, leave, push, pop, pusha, popa, pushf, and popf instructions default to 32-bit size. This is so that the stack pointer is manipulated in the same way over function calls, allowing access to function parameters at the same stack offsets as in 32-bit mode. .code16gcc also automatically adds address size prefixes where necessary to use the 32-bit addressing modes that gcc generates.

The code which as generates in 16-bit mode will not necessarily run on a 16-bit pre-80386 processor. To write code that runs on such a processor, you must refrain from using any 32-bit constructs which require as to output address or operand size prefixes.

Note that writing 16-bit code instructions by explicitly specifying a prefix or an instruction mnemonic suffix within a 32-bit code section generates different machine instructions than those generated for a 16-bit code segment. In a 32-bit code section, the following code generates the machine opcode bytes 66 6a 04, which pushes the value 4 onto the stack, decrementing %esp by 2. 

        pushw $4

The same code in a 16-bit code section would generate the machine opcode bytes 6a 04 (ie. without the operand size prefix), which is correct since the processor default operand size is assumed to be 16 bits in a 16-bit code section.

Node:i386-Bugs, Next:, Previous:i386-Arch, Up:i386-Dependent

AT&T Syntax bugs

The UnixWare assembler, and probably other AT&T derived ix86 Unix assemblers, generate floating point instructions with reversed source and destination registers in certain cases. Unfortunately, gcc and possibly many other programs use this reversed syntax, so we're stuck with it.

For example 

        fsub %st,%st(3)

results in %st(3) being updated to %st - %st(3) rather than the expected %st(3) - %st. This happens with all the non-commutative arithmetic floating point operations with two register operands where the source register is %st and the destination register is %st(i).

Node:i386-Arch, Next:, Previous:i386-16bit, Up:i386-Dependent

Specifying CPU Architecture

as may be told to assemble for a particular CPU architecture with the .arch cpu_type directive. This directive enables a warning when gas detects an instruction that is not supported on the CPU specified. The choices for cpu_type are:

i8086 i186 i286 i386
i486 i586 i686 pentium
pentiumpro pentium4 k6 athlon
sledgehammer

Apart from the warning, there are only two other effects on as operation; Firstly, if you specify a CPU other than i486, then shift by one instructions such as sarl $1, %eax will automatically use a two byte opcode sequence. The larger three byte opcode sequence is used on the 486 (and when no architecture is specified) because it executes faster on the 486. Note that you can explicitly request the two byte opcode by writing sarl %eax. Secondly, if you specify i8086, i186, or i286, and .code16 or .code16gcc then byte offset conditional jumps will be promoted when necessary to a two instruction sequence consisting of a conditional jump of the opposite sense around an unconditional jump to the target.

Following the CPU architecture, you may specify jumps or nojumps to control automatic promotion of conditional jumps. jumps is the default, and enables jump promotion; All external jumps will be of the long variety, and file-local jumps will be promoted as necessary. (see i386-Jumps) nojumps leaves external conditional jumps as byte offset jumps, and warns about file-local conditional jumps that as promotes. Unconditional jumps are treated as for jumps.

For example 

 .arch i8086,nojumps

Node:i386-Notes, Previous:i386-Bugs, Up:i386-Dependent

Notes

There is some trickery concerning the mul and imul instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding multiplies (base opcode 0xf6; extension 4 for mul and 5 for imul) can be output only in the one operand form. Thus, imul %ebx, %eax does not select the expanding multiply; the expanding multiply would clobber the %edx register, and this would confuse gcc output. Use imul %ebx to get the 64-bit product in %edx:%eax.

We have added a two operand form of imul when the first operand is an immediate mode expression and the second operand is a register. This is just a shorthand, so that, multiplying %eax by 69, for example, can be done with imul $69, %eax rather than imul $69, %eax, %eax.

Node:i860-Dependent, Next:, Previous:i386-Dependent, Up:Machine Dependencies

Intel i860 Dependent Features

Node:Notes-i860, Next:, Up:i860-Dependent

i860 Notes

This is a fairly complete i860 assembler which is compatible with the UNIX System V/860 Release 4 assembler. However, it does not currently support SVR4 PIC (i.e., @GOT, @GOTOFF, @PLT).

Like the SVR4/860 assembler, the output object format is ELF32. Currently, this is the only supported object format. If there is sufficient interest, other formats such as COFF may be implemented.

Node:Options-i860, Next:, Previous:Notes-i860, Up:i860-Dependent

i860 Command-line Options

SVR4 compatibility options

-V
Print assembler version.
-Qy
Ignored.
-Qn
Ignored.

Other options

-EL
Select little endian output (this is the default).
-EB
Select big endian output. Note that the i860 always reads instructions as little endian data, so this option only effects data and not instructions.
-mwarn-expand
Emit a warning message if any pseudo-instruction expansions occurred. For example, a or instruction with an immediate larger than 16-bits will be expanded into two instructions. This is a very undesirable feature to rely on, so this flag can help detect any code where it happens. One use of it, for instance, has been to find and eliminate any place where gcc may emit these pseudo-instructions.

Node:Directives-i860, Next:, Previous:Options-i860, Up:i860-Dependent

i860 Machine Directives

.dual
Enter dual instruction mode. While this directive is supported, the preferred way to use dual instruction mode is to explicitly code the dual bit with the d. prefix.
.enddual
Exit dual instruction mode. While this directive is supported, the preferred way to use dual instruction mode is to explicitly code the dual bit with the d. prefix.
.atmp
Change the temporary register used when expanding pseudo operations. The default register is r31.

Node:Opcodes for i860, Previous:Directives-i860, Up:i860-Dependent

i860 Opcodes

All of the Intel i860 machine instructions are supported. Please see either i860 Microprocessor Programmer's Reference Manual or i860 Microprocessor Architecture for more information.

Other instruction support (pseudo-instructions)

For compatibility with some other i860 assemblers, a number of pseudo-instructions are supported. While these are supported, they are a very undesirable feature that should be avoided - in particular, when they result in an expansion to multiple actual i860 instructions. Below are the pseudo-instructions that result in expansions.

Node:i960-Dependent, Next:, Previous:i860-Dependent, Up:Machine Dependencies

Intel 80960 Dependent Features

Node:Options-i960, Next:, Up:i960-Dependent

i960 Command-line Options


-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC
Select the 80960 architecture. Instructions or features not supported by the selected architecture cause fatal errors.

-ACA is equivalent to -ACA_A; -AKC is equivalent to -AMC. Synonyms are provided for compatibility with other tools.

If you do not specify any of these options, as generates code for any instruction or feature that is supported by some version of the 960 (even if this means mixing architectures!). In principle, as attempts to deduce the minimal sufficient processor type if none is specified; depending on the object code format, the processor type may be recorded in the object file. If it is critical that the as output match a specific architecture, specify that architecture explicitly.

-b
Add code to collect information about conditional branches taken, for later optimization using branch prediction bits. (The conditional branch instructions have branch prediction bits in the CA, CB, and CC architectures.) If BR represents a conditional branch instruction, the following represents the code generated by the assembler when -b is specified: 
        call    increment routine
        .word   0       # pre-counter
Label:  BR
        call    increment routine
        .word   0       # post-counter

The counter following a branch records the number of times that branch was not taken; the differenc between the two counters is the number of times the branch was taken.

A table of every such Label is also generated, so that the external postprocessor gbr960 (supplied by Intel) can locate all the counters. This table is always labelled __BRANCH_TABLE__; this is a local symbol to permit collecting statistics for many separate object files. The table is word aligned, and begins with a two-word header. The first word, initialized to 0, is used in maintaining linked lists of branch tables. The second word is a count of the number of entries in the table, which follow immediately: each is a word, pointing to one of the labels illustrated above. 

 +------------+------------+------------+ ... +------------+
 |            |            |            |     |            |
 |  *NEXT     |  COUNT: N  | *BRLAB 1   |     | *BRLAB N   |
 |            |            |            |     |            |
 +------------+------------+------------+ ... +------------+

               __BRANCH_TABLE__ layout

The first word of the header is used to locate multiple branch tables, since each object file may contain one. Normally the links are maintained with a call to an initialization routine, placed at the beginning of each function in the file. The GNU C compiler generates these calls automatically when you give it a -b option. For further details, see the documentation of gbr960.

-no-relax
Normally, Compare-and-Branch instructions with targets that require displacements greater than 13 bits (or that have external targets) are replaced with the corresponding compare (or chkbit) and branch instructions. You can use the -no-relax option to specify that as should generate errors instead, if the target displacement is larger than 13 bits.

This option does not affect the Compare-and-Jump instructions; the code emitted for them is always adjusted when necessary (depending on displacement size), regardless of whether you use -no-relax.

Node:Floating Point-i960, Next:, Previous:Options-i960, Up:i960-Dependent

Floating Point

as generates IEEE floating-point numbers for the directives .float, .double, .extended, and .single.

Node:Directives-i960, Next:, Previous:Floating Point-i960, Up:i960-Dependent

i960 Machine Directives

.bss symbol, length, align
Reserve length bytes in the bss section for a local symbol, aligned to the power of two specified by align. length and align must be positive absolute expressions. This directive differs from .lcomm only in that it permits you to specify an alignment. See .lcomm.
.extended flonums
.extended expects zero or more flonums, separated by commas; for each flonum, .extended emits an IEEE extended-format (80-bit) floating-point number.
.leafproc call-lab, bal-lab
You can use the .leafproc directive in conjunction with the optimized callj instruction to enable faster calls of leaf procedures. If a procedure is known to call no other procedures, you may define an entry point that skips procedure prolog code (and that does not depend on system-supplied saved context), and declare it as the bal-lab using .leafproc. If the procedure also has an entry point that goes through the normal prolog, you can specify that entry point as call-lab.

A .leafproc declaration is meant for use in conjunction with the optimized call instruction callj; the directive records the data needed later to choose between converting the callj into a bal or a call.

call-lab is optional; if only one argument is present, or if the two arguments are identical, the single argument is assumed to be the bal entry point.

.sysproc name, index
The .sysproc directive defines a name for a system procedure. After you define it using .sysproc, you can use name to refer to the system procedure identified by index when calling procedures with the optimized call instruction callj.

Both arguments are required; index must be between 0 and 31 (inclusive).

Node:Opcodes for i960, Previous:Directives-i960, Up:i960-Dependent

i960 Opcodes

All Intel 960 machine instructions are supported; see i960 Command-line Options for a discussion of selecting the instruction subset for a particular 960 architecture.

Some opcodes are processed beyond simply emitting a single corresponding instruction: callj, and Compare-and-Branch or Compare-and-Jump instructions with target displacements larger than 13 bits.

Node:callj-i960, Next:, Up:Opcodes for i960

callj

You can write callj to have the assembler or the linker determine the most appropriate form of subroutine call: call, bal, or calls. If the assembly source contains enough information--a .leafproc or .sysproc directive defining the operand--then as translates the callj; if not, it simply emits the callj, leaving it for the linker to resolve.

Node:Compare-and-branch-i960, Previous:callj-i960, Up:Opcodes for i960

Compare-and-Branch

The 960 architectures provide combined Compare-and-Branch instructions that permit you to store the branch target in the lower 13 bits of the instruction word itself. However, if you specify a branch target far enough away that its address won't fit in 13 bits, the assembler can either issue an error, or convert your Compare-and-Branch instruction into separate instructions to do the compare and the branch.

Whether as gives an error or expands the instruction depends on two choices you can make: whether you use the -no-relax option, and whether you use a "Compare and Branch" instruction or a "Compare and Jump" instruction. The "Jump" instructions are always expanded if necessary; the "Branch" instructions are expanded when necessary unless you specify -no-relax--in which case as gives an error instead.

These are the Compare-and-Branch instructions, their "Jump" variants, and the instruction pairs they may expand into: 

        Compare and
     Branch      Jump       Expanded to
     ------    ------       ------------
        bbc                 chkbit; bno
        bbs                 chkbit; bo
     cmpibe    cmpije       cmpi; be
     cmpibg    cmpijg       cmpi; bg
    cmpibge   cmpijge       cmpi; bge
     cmpibl    cmpijl       cmpi; bl
    cmpible   cmpijle       cmpi; ble
    cmpibno   cmpijno       cmpi; bno
    cmpibne   cmpijne       cmpi; bne
     cmpibo    cmpijo       cmpi; bo
     cmpobe    cmpoje       cmpo; be
     cmpobg    cmpojg       cmpo; bg
    cmpobge   cmpojge       cmpo; bge
     cmpobl    cmpojl       cmpo; bl
    cmpoble   cmpojle       cmpo; ble
    cmpobne   cmpojne       cmpo; bne

Node:M32R-Dependent, Next:, Previous:i960-Dependent, Up:Machine Dependencies

M32R Dependent Features

Node:M32R-Opts, Next:, Up:M32R-Dependent

M32R Options

The Mitsubishi M32R version of as has a few machine dependent options:

-m32rx
as can assemble code for several different members of the Mitsubishi M32R family. Normally the default is to assemble code for the M32R microprocessor. This option may be used to change the default to the M32RX microprocessor, which adds some more instructions to the basic M32R instruction set, and some additional parameters to some of the original instructions.
-m32r
This option can be used to restore the assembler's default behaviour of assembling for the M32R microprocessor. This can be useful if the default has been changed by a previous command line option.
-warn-explicit-parallel-conflicts
Instructs as to produce warning messages when questionable parallel instructions are encountered. This option is enabled by default, but gcc disables it when it invokes as directly. Questionable instructions are those whoes behaviour would be different if they were executed sequentially. For example the code fragment mv r1, r2 || mv r3, r1 produces a different result from mv r1, r2 \n mv r3, r1 since the former moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 and r3.
-Wp
This is a shorter synonym for the -warn-explicit-parallel-conflicts option.
-no-warn-explicit-parallel-conflicts
Instructs as not to produce warning messages when questionable parallel instructions are encountered.
-Wnp
This is a shorter synonym for the -no-warn-explicit-parallel-conflicts option.

Node:M32R-Warnings, Previous:M32R-Opts, Up:M32R-Dependent

M32R Warnings

There are several warning and error messages that can be produced by as which are specific to the M32R:


output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?
This message is only produced if warnings for explicit parallel conflicts have been enabled. It indicates that the assembler has encountered a parallel instruction in which the destination register of the left hand instruction is used as an input register in the right hand instruction. For example in this code fragment mv r1, r2 || neg r3, r1 register r1 is the destination of the move instruction and the input to the neg instruction.
output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?
This message is only produced if warnings for explicit parallel conflicts have been enabled. It indicates that the assembler has encountered a parallel instruction in which the destination register of the right hand instruction is used as an input register in the left hand instruction. For example in this code fragment mv r1, r2 || neg r2, r3 register r2 is the destination of the neg instruction and the input to the move instruction.
instruction ... is for the M32RX only
This message is produced when the assembler encounters an instruction which is only supported by the M32Rx processor, and the -m32rx command line flag has not been specified to allow assembly of such instructions.
unknown instruction ...
This message is produced when the assembler encounters an instruction which it doe snot recognise.
only the NOP instruction can be issued in parallel on the m32r
This message is produced when the assembler encounters a parallel instruction which does not involve a NOP instruction and the -m32rx command line flag has not been specified. Only the M32Rx processor is able to execute two instructions in parallel.
instruction ... cannot be executed in parallel.
This message is produced when the assembler encounters a parallel instruction which is made up of one or two instructions which cannot be executed in parallel.
Instructions share the same execution pipeline
This message is produced when the assembler encounters a parallel instruction whoes components both use the same execution pipeline.
Instructions write to the same destination register.
This message is produced when the assembler encounters a parallel instruction where both components attempt to modify the same register. For example these code fragments will produce this message: mv r1, r2 || neg r1, r3 jl r0 || mv r14, r1 st r2, @-r1 || mv r1, r3 mv r1, r2 || ld r0, @r1+ cmp r1, r2 || addx r3, r4 (Both write to the condition bit)

Node:M68K-Dependent, Next:, Previous:M32R-Dependent, Up:Machine Dependencies

M680x0 Dependent Features

Node:M68K-Opts, Next:, Up:M68K-Dependent

M680x0 Options

The Motorola 680x0 version of as has a few machine dependent options:


-l
You can use the -l option to shorten the size of references to undefined symbols. If you do not use the -l option, references to undefined symbols are wide enough for a full long (32 bits). (Since as cannot know where these symbols end up, as can only allocate space for the linker to fill in later. Since as does not know how far away these symbols are, it allocates as much space as it can.) If you use this option, the references are only one word wide (16 bits). This may be useful if you want the object file to be as small as possible, and you know that the relevant symbols are always less than 17 bits away.
--register-prefix-optional
For some configurations, especially those where the compiler normally does not prepend an underscore to the names of user variables, the assembler requires a % before any use of a register name. This is intended to let the assembler distinguish between C variables and functions named a0 through a7, and so on. The % is always accepted, but is not required for certain configurations, notably sun3. The --register-prefix-optional option may be used to permit omitting the % even for configurations for which it is normally required. If this is done, it will generally be impossible to refer to C variables and functions with the same names as register names.
--bitwise-or
Normally the character | is treated as a comment character, which means that it can not be used in expressions. The --bitwise-or option turns | into a normal character. In this mode, you must either use C style comments, or start comments with a # character at the beginning of a line.
--base-size-default-16 --base-size-default-32
If you use an addressing mode with a base register without specifying the size, as will normally use the full 32 bit value. For example, the addressing mode %a0@(%d0) is equivalent to %a0@(%d0:l). You may use the --base-size-default-16 option to tell as to default to using the 16 bit value. In this case, %a0@(%d0) is equivalent to %a0@(%d0:w). You may use the --base-size-default-32 option to restore the default behaviour.
--disp-size-default-16 --disp-size-default-32
If you use an addressing mode with a displacement, and the value of the displacement is not known, as will normally assume that the value is 32 bits. For example, if the symbol disp has not been defined, as will assemble the addressing mode %a0@(disp,%d0) as though disp is a 32 bit value. You may use the --disp-size-default-16 option to tell as to instead assume that the displacement is 16 bits. In this case, as will assemble %a0@(disp,%d0) as though disp is a 16 bit value. You may use the --disp-size-default-32 option to restore the default behaviour.
--pcrel
Always keep branches PC-relative. In the M680x0 architecture all branches are defined as PC-relative. However, on some processors they are limited to word displacements maximum. When as needs a long branch that is not available, it normally emits an absolute jump instead. This option disables this substitution. When this option is given and no long branches are available, only word branches will be emitted. An error message will be generated if a word branch cannot reach its target. This option has no effect on 68020 and other processors that have long branches. see Branch Improvement.
-m68000
as can assemble code for several different members of the Motorola 680x0 family. The default depends upon how as was configured when it was built; normally, the default is to assemble code for the 68020 microprocessor. The following options may be used to change the default. These options control which instructions and addressing modes are permitted. The members of the 680x0 family are very similar. For detailed information about the differences, see the Motorola manuals.
-m68000
-m68ec000
-m68hc000
-m68hc001
-m68008
-m68302
-m68306
-m68307
-m68322
-m68356
Assemble for the 68000. -m68008, -m68302, and so on are synonyms for -m68000, since the chips are the same from the point of view of the assembler.
-m68010
Assemble for the 68010.
-m68020
-m68ec020
Assemble for the 68020. This is normally the default.
-m68030
-m68ec030
Assemble for the 68030.
-m68040
-m68ec040
Assemble for the 68040.
-m68060
-m68ec060
Assemble for the 68060.
-mcpu32
-m68330
-m68331
-m68332
-m68333
-m68334
-m68336
-m68340
-m68341
-m68349
-m68360
Assemble for the CPU32 family of chips.
-m5200
Assemble for the ColdFire family of chips.
-m68881
-m68882
Assemble 68881 floating point instructions. This is the default for the 68020, 68030, and the CPU32. The 68040 and 68060 always support floating point instructions.
-mno-68881
Do not assemble 68881 floating point instructions. This is the default for 68000 and the 68010. The 68040 and 68060 always support floating point instructions, even if this option is used.
-m68851
Assemble 68851 MMU instructions. This is the default for the 68020, 68030, and 68060. The 68040 accepts a somewhat different set of MMU instructions; -m68851 and -m68040 should not be used together.
-mno-68851
Do not assemble 68851 MMU instructions. This is the default for the 68000, 68010, and the CPU32. The 68040 accepts a somewhat different set of MMU instructions.

Node:M68K-Syntax, Next:, Previous:M68K-Opts, Up:M68K-Dependent

Syntax

This syntax for the Motorola 680x0 was developed at MIT.

The 680x0 version of as uses instructions names and syntax compatible with the Sun assembler. Intervening periods are ignored; for example, movl is equivalent to mov.l.

In the following table apc stands for any of the address registers (%a0 through %a7), the program counter (%pc), the zero-address relative to the program counter (%zpc), a suppressed address register (%za0 through %za7), or it may be omitted entirely. The use of size means one of w or l, and it may be omitted, along with the leading colon, unless a scale is also specified. The use of scale means one of 1, 2, 4, or 8, and it may always be omitted along with the leading colon.

The following addressing modes are understood:

Immediate
#number
Data Register
%d0 through %d7
Address Register
%a0 through %a7
%a7 is also known as %sp, i.e. the Stack Pointer. %a6 is also known as %fp, the Frame Pointer.
Address Register Indirect
%a0@ through %a7@
Address Register Postincrement
%a0@+ through %a7@+
Address Register Predecrement
%a0@- through %a7@-
Indirect Plus Offset
apc@(number)
Index
apc@(number,register:size:scale)

The number may be omitted.

Postindex
apc@(number)@(onumber,register:size:scale)

The onumber or the register, but not both, may be omitted.

Preindex
apc@(number,register:size:scale)@(onumber)

The number may be omitted. Omitting the register produces the Postindex addressing mode.

Absolute
symbol, or digits, optionally followed by :b, :w, or :l.

Node:M68K-Moto-Syntax, Next:, Previous:M68K-Syntax, Up:M68K-Dependent

Motorola Syntax

The standard Motorola syntax for this chip differs from the syntax already discussed (see Syntax). as can accept Motorola syntax for operands, even if MIT syntax is used for other operands in the same instruction. The two kinds of syntax are fully compatible.

In the following table apc stands for any of the address registers (%a0 through %a7), the program counter (%pc), the zero-address relative to the program counter (%zpc), or a suppressed address register (%za0 through %za7). The use of size means one of w or l, and it may always be omitted along with the leading dot. The use of scale means one of 1, 2, 4, or 8, and it may always be omitted along with the leading asterisk.

The following additional addressing modes are understood:

Address Register Indirect
(%a0) through (%a7)
%a7 is also known as %sp, i.e. the Stack Pointer. %a6 is also known as %fp, the Frame Pointer.
Address Register Postincrement
(%a0)+ through (%a7)+
Address Register Predecrement
-(%a0) through -(%a7)
Indirect Plus Offset
number(%a0) through number(%a7), or number(%pc).

The number may also appear within the parentheses, as in (number,%a0). When used with the pc, the number may be omitted (with an address register, omitting the number produces Address Register Indirect mode).

Index
number(apc,register.size*scale)

The number may be omitted, or it may appear within the parentheses. The apc may be omitted. The register and the apc may appear in either order. If both apc and register are address registers, and the size and scale are omitted, then the first register is taken as the base register, and the second as the index register.

Postindex
([number,apc],register.size*scale,onumber)

The onumber, or the register, or both, may be omitted. Either the number or the apc may be omitted, but not both.

Preindex
([number,apc,register.size*scale],onumber)

The number, or the apc, or the register, or any two of them, may be omitted. The onumber may be omitted. The register and the apc may appear in either order. If both apc and register are address registers, and the size and scale are omitted, then the first register is taken as the base register, and the second as the index register.

Node:M68K-Float, Next:, Previous:M68K-Moto-Syntax, Up:M68K-Dependent

Floating Point

Packed decimal (P) format floating literals are not supported. Feel free to add the code!

The floating point formats generated by directives are these.

.float
Single precision floating point constants.
.double
Double precision floating point constants.
.extend
.ldouble
Extended precision (long double) floating point constants.

Node:M68K-Directives, Next:, Previous:M68K-Float, Up:M68K-Dependent

680x0 Machine Directives

In order to be compatible with the Sun assembler the 680x0 assembler understands the following directives.

.data1
This directive is identical to a .data 1 directive.
.data2
This directive is identical to a .data 2 directive.
.even
This directive is a special case of the .align directive; it aligns the output to an even byte boundary.
.skip
This directive is identical to a .space directive.

Node:M68K-opcodes, Previous:M68K-Directives, Up:M68K-Dependent

Opcodes

Node:M68K-Branch, Next:, Up:M68K-opcodes

Branch Improvement

Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by substituting j for b at the start of a Motorola mnemonic.

The following table summarizes the pseudo-operations. A * flags cases that are more fully described after the table: 

          Displacement
          +------------------------------------------------------------
          |                68020           68000/10, not PC-relative OK
Pseudo-Op |BYTE    WORD    LONG            ABSOLUTE LONG JUMP    **
          +------------------------------------------------------------
     jbsr |bsrs    bsrw    bsrl            jsr
      jra |bras    braw    bral            jmp
*     jXX |bXXs    bXXw    bXXl            bNXs;jmp
*    dbXX | N/A    dbXXw   dbXX;bras;bral  dbXX;bras;jmp
     fjXX | N/A    fbXXw   fbXXl            N/A

XX: condition
NX: negative of condition XX

*--see full description below

**--this expansion mode is disallowed by --pcrel

jbsr
jra
These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target. This instruction will be a byte or word branch is that is sufficient. Otherwise, a long branch will be emitted if available. If no long branches are available and the --pcrel option is not given, an absolute long jump will be emitted instead. If no long branches are available, the --pcrel option is given, and a word branch cannot reach the target, an error message is generated.

In addition to standard branch operands, as allows these pseudo-operations to have all operands that are allowed for jsr and jmp, substituting these instructions if the operand given is not valid for a branch instruction.

jXX
Here, jXX stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test. The full list of pseudo-ops in this family is: 
 jhi   jls   jcc   jcs   jne   jeq   jvc
 jvs   jpl   jmi   jge   jlt   jgt   jle

Usually, each of these pseudo-operations expands to a single branch instruction. However, if a word branch is not sufficient, no long branches are available, and the --pcrel option is not given, as issues a longer code fragment in terms of NX, the opposite condition to XX. For example, under these conditions: 

    jXX foo
gives 
     bNXs oof
     jmp foo
 oof:

dbXX
The full family of pseudo-operations covered here is 
 dbhi   dbls   dbcc   dbcs   dbne   dbeq   dbvc
 dbvs   dbpl   dbmi   dbge   dblt   dbgt   dble
 dbf    dbra   dbt

Motorola dbXX instructions allow word displacements only. When a word displacement is sufficient, each of these pseudo-operations expands to the corresponding Motorola instruction. When a word displacement is not sufficient and long branches are available, when the source reads dbXX foo, as emits 

     dbXX oo1
     bras oo2
 oo1:bral foo
 oo2:

If, however, long branches are not available and the --pcrel option is not given, as emits 

     dbXX oo1
     bras oo2
 oo1:jmp foo
 oo2:

fjXX
This family includes 
 fjne   fjeq   fjge   fjlt   fjgt   fjle   fjf
 fjt    fjgl   fjgle  fjnge  fjngl  fjngle fjngt
 fjnle  fjnlt  fjoge  fjogl  fjogt  fjole  fjolt
 fjor   fjseq  fjsf   fjsne  fjst   fjueq  fjuge
 fjugt  fjule  fjult  fjun

Each of these pseudo-operations always expands to a single Motorola coprocessor branch instruction, word or long. All Motorola coprocessor branch instructions allow both word and long displacements.

Node:M68K-Chars, Previous:M68K-Branch, Up:M68K-opcodes

Special Characters

The immediate character is # for Sun compatibility. The line-comment character is | (unless the --bitwise-or option is used). If a # appears at the beginning of a line, it is treated as a comment unless it looks like # line file, in which case it is treated normally.

Node:M68HC11-Dependent, Next:, Previous:M68K-Dependent, Up:Machine Dependencies

M68HC11 and M68HC12 Dependent Features

Node:M68HC11-Opts, Next:, Up:M68HC11-Dependent

M68HC11 and M68HC12 Options

The Motorola 68HC11 and 68HC12 version of as has a few machine dependent options.

This option switches the assembler in the M68HC11 mode. In this mode, the assembler only accepts 68HC11 operands and mnemonics. It produces code for the 68HC11.

This option switches the assembler in the M68HC12 mode. In this mode, the assembler also accepts 68HC12 operands and mnemonics. It produces code for the 68HC12. A fiew 68HC11 instructions are replaced by some 68HC12 instructions as recommended by Motorola specifications.

You can use the --strict-direct-mode option to disable the automatic translation of direct page mode addressing into extended mode when the instruction does not support direct mode. For example, the clr instruction does not support direct page mode addressing. When it is used with the direct page mode, as will ignore it and generate an absolute addressing. This option prevents as from doing this, and the wrong usage of the direct page mode will raise an error.

The --short-branchs option turns off the translation of relative branches into absolute branches when the branch offset is out of range. By default as transforms the relative branch (bsr, bgt, bge, beq, bne, ble, blt, bhi, bcc, bls, bcs, bmi, bvs, bvs, bra) into an absolute branch when the offset is out of the -128 .. 127 range. In that case, the bsr instruction is translated into a jsr, the bra instruction is translated into a jmp and the conditional branchs instructions are inverted and followed by a jmp. This option disables these translations and as will generate an error if a relative branch is out of range. This option does not affect the optimization associated to the jbra, jbsr and jbXX pseudo opcodes.

The --force-long-branchs option forces the translation of relative branches into absolute branches. This option does not affect the optimization associated to the jbra, jbsr and jbXX pseudo opcodes.

You can use the --print-insn-syntax option to obtain the syntax description of the instruction when an error is detected.

The --print-opcodes option prints the list of all the instructions with their syntax. The first item of each line represents the instruction name and the rest of the line indicates the possible operands for that instruction. The list is printed in alphabetical order. Once the list is printed as exits.

The --generate-example option is similar to --print-opcodes but it generates an example for each instruction instead.

Node:M68HC11-Syntax, Next:, Previous:M68HC11-Opts, Up:M68HC11-Dependent

Syntax

In the M68HC11 syntax, the instruction name comes first and it may be followed by one or several operands (up to three). Operands are separated by comma (,). In the normal mode, as will complain if too many operands are specified for a given instruction. In the MRI mode (turned on with -M option), it will treat them as comments. Example: 

inx
lda  #23
bset 2,x #4
brclr *bot #8 foo

The following addressing modes are understood:

Immediate
#number
Address Register
number,X, number,Y

The number may be omitted in which case 0 is assumed.

Direct Addressing mode
*symbol, or *digits
Absolute
symbol, or digits

Node:M68HC11-Float, Next:, Previous:M68HC11-Syntax, Up:M68HC11-Dependent

Floating Point

Packed decimal (P) format floating literals are not supported. Feel free to add the code!

The floating point formats generated by directives are these.

.float
Single precision floating point constants.
.double
Double precision floating point constants.
.extend
.ldouble
Extended precision (long double) floating point constants.

Node:M68HC11-opcodes, Previous:M68HC11-Float, Up:M68HC11-Dependent

Opcodes

Node:M68HC11-Branch, Up:M68HC11-opcodes

Branch Improvement

Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by prepending j to the start of Motorola mnemonic. These pseudo opcodes are not affected by the --short-branchs or --force-long-branchs options.

The following table summarizes the pseudo-operations. 

                              Displacement Width
          +-------------------------------------------------------------+
          |                     Options                                 |
          |    --short-branchs            --force-long-branchs          |
          +--------------------------+----------------------------------+
Pseudo-Op |BYTE             WORD     | BYTE          WORD               |
          +--------------------------+----------------------------------+
      bsr | bsr <pc-rel>    <error>  |               jsr <abs>          |
      bra | bra <pc-rel>    <error>  |               jmp <abs>          |
     jbsr | bsr <pc-rel>   jsr <abs> | bsr <pc-rel>  jsr <abs>          |
     jbra | bra <pc-rel>   jmp <abs> | bra <pc-rel>  jmp <abs>          |
      bXX | bXX <pc-rel>    <error>  |               bNX +3; jmp <abs>  |
     jbXX | bXX <pc-rel>   bNX +3;   | bXX <pc-rel>  bNX +3; jmp <abs>  |
          |                jmp <abs> |                                  |
          +--------------------------+----------------------------------+
XX: condition
NX: negative of condition XX
jbsr
jbra
These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target.
jbXX
Here, jbXX stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test. The full list of pseudo-ops in this family is: 
 jbcc   jbeq   jbge   jbgt   jbhi   jbvs   jbpl  jblo
 jbcs   jbne   jblt   jble   jbls   jbvc   jbmi

For the cases of non-PC relative displacements and long displacements, as issues a longer code fragment in terms of NX, the opposite condition to XX. For example, for the non-PC relative case: 

    jbXX foo
gives 
     bNXs oof
     jmp foo
 oof:

Node:M88K-Dependent, Next:, Previous:M68HC11-Dependent, Up:Machine Dependencies

Motorola M88K Dependent Features

Node:M88K Directives, Up:M88K-Dependent

M88K Machine Directives

The M88K version of the assembler supports the following machine directives:

.align
This directive aligns the section program counter on the next 4-byte boundary.
.dfloat expr
This assembles a double precision (64-bit) floating point constant.
.ffloat expr
This assembles a single precision (32-bit) floating point constant.
.half expr
This directive assembles a half-word (16-bit) constant.
.word expr
This assembles a word (32-bit) constant.
.string "str"
This directive behaves like the standard .ascii directive for copying str into the object file. The string is not terminated with a null byte.
.set symbol, value
This directive creates a symbol named symbol which is an alias for another symbol (possibly not yet defined). This should not be confused with the mnemonic set, which is a legitimate M88K instruction.
.def symbol, value
This directive is synonymous with .set and is presumably provided for compatibility with other M88K assemblers.
.bss symbol, length, align
Reserve length bytes in the bss section for a local symbol, aligned to the power of two specified by align. length and align must be positive absolute expressions. This directive differs from .lcomm only in that it permits you to specify an alignment. See .lcomm.

Node:MIPS-Dependent, Next:, Previous:M88K-Dependent, Up:Machine Dependencies

MIPS Dependent Features

GNU as for MIPS architectures supports several different MIPS processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For information about the MIPS instruction set, see MIPS RISC Architecture, by Kane and Heindrich (Prentice-Hall). For an overview of MIPS assembly conventions, see "Appendix D: Assembly Language Programming" in the same work.

Node:MIPS Opts, Next:, Up:MIPS-Dependent

Assembler options

The MIPS configurations of GNU as support these special options:

-G num
This option sets the largest size of an object that can be referenced implicitly with the gp register. It is only accepted for targets that use ECOFF format. The default value is 8.
-EB
-EL
Any MIPS configuration of as can select big-endian or little-endian output at run time (unlike the other GNU development tools, which must be configured for one or the other). Use -EB to select big-endian output, and -EL for little-endian.
-mips1
-mips2
-mips3
-mips4
-mips5
-mips32
-mips64
Generate code for a particular MIPS Instruction Set Architecture level. -mips1 corresponds to the R2000 and R3000 processors, -mips2 to the R6000 processor, -mips3 to the R4000 processor, and -mips4 to the R8000 and R10000 processors. -mips5, -mips32, and -mips64 correspond to generic MIPS V, MIPS32, and MIPS64 ISA processors, respectively. You can also switch instruction sets during the assembly; see Directives to override the ISA level.
-mgp32
-mfp32
Some macros have different expansions for 32-bit and 64-bit registers. The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers.

On some MIPS variants there is a 32-bit mode flag; when this flag is set, 64-bit instructions generate a trap. Also, some 32-bit OSes only save the 32-bit registers on a context switch, so it is essential never to use the 64-bit registers.

-mgp64
Assume that 64-bit general purpose registers are available. This is provided in the interests of symmetry with -gp32.
-mips16
-no-mips16
Generate code for the MIPS 16 processor. This is equivalent to putting .set mips16 at the start of the assembly file. -no-mips16 turns off this option.
-mfix7000
-no-mfix7000
Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.
-m4010
-no-m4010
Generate code for the LSI R4010 chip. This tells the assembler to accept the R4010 specific instructions (addciu, ffc, etc.), and to not schedule nop instructions around accesses to the HI and LO registers. -no-m4010 turns off this option.
-m4650
-no-m4650
Generate code for the MIPS R4650 chip. This tells the assembler to accept the mad and madu instruction, and to not schedule nop instructions around accesses to the HI and LO registers. -no-m4650 turns off this option.
-m3900
-no-m3900
-m4100
-no-m4100
For each option -mnnnn, generate code for the MIPS RNNNN chip. This tells the assembler to accept instructions specific to that chip, and to schedule for that chip's hazards.
-march=cpu
Generate code for a particular MIPS cpu. It is exactly equivalent to -mcpu, except that there are more value of cpu understood. Valid cpu value are:
2000, 3000, 3900, 4000, 4010, 4100, 4111, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, 6000, rm7000, 8000, 10000, 12000, mips32-4k, sb1

-mtune=cpu
Schedule and tune for a particular MIPS cpu. Valid cpu values are identical to -march=cpu.
-mcpu=cpu
Generate code and schedule for a particular MIPS cpu. This is exactly equivalent to -march=cpu and -mtune=cpu. Valid cpu values are identical to -march=cpu. Use of this option is discouraged.
-nocpp
This option is ignored. It is accepted for command-line compatibility with other assemblers, which use it to turn off C style preprocessing. With GNU as, there is no need for -nocpp, because the GNU assembler itself never runs the C preprocessor.
--construct-floats
--no-construct-floats
The --no-construct-floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. This feature is useful if the processor support the FR bit in its status register, and this bit is known (by the programmer) to be set. This bit prevents the aliasing of the double width register by the single width registers.

By default --construct-floats is selected, allowing construction of these floating point constants.

--trap
--no-break
as automatically macro expands certain division and multiplication instructions to check for overflow and division by zero. This option causes as to generate code to take a trap exception rather than a break exception when an error is detected. The trap instructions are only supported at Instruction Set Architecture level 2 and higher.
--break
--no-trap
Generate code to take a break exception rather than a trap exception when an error is detected. This is the default.
-n
When this option is used, as will issue a warning every time it generates a nop instruction from a macro.

Node:MIPS Object, Next:, Previous:MIPS Opts, Up:MIPS-Dependent

MIPS ECOFF object code

Assembling for a MIPS ECOFF target supports some additional sections besides the usual .text, .data and .bss. The additional sections are .rdata, used for read-only data, .sdata, used for small data, and .sbss, used for small common objects.

When assembling for ECOFF, the assembler uses the $gp ($28) register to form the address of a "small object". Any object in the .sdata or .sbss sections is considered "small" in this sense. For external objects, or for objects in the .bss section, you can use the gcc -G option to control the size of objects addressed via $gp; the default value is 8, meaning that a reference to any object eight bytes or smaller uses $gp. Passing -G 0 to as prevents it from using the $gp register on the basis of object size (but the assembler uses $gp for objects in .sdata or sbss in any case). The size of an object in the .bss section is set by the .comm or .lcomm directive that defines it. The size of an external object may be set with the .extern directive. For example, .extern sym,4 declares that the object at sym is 4 bytes in length, whie leaving sym otherwise undefined.

Using small ECOFF objects requires linker support, and assumes that the $gp register is correctly initialized (normally done automatically by the startup code). MIPS ECOFF assembly code must not modify the $gp register.

Node:MIPS Stabs, Next:, Previous:MIPS Object, Up:MIPS-Dependent

Directives for debugging information

MIPS ECOFF as supports several directives used for generating debugging information which are not support by traditional MIPS assemblers. These are .def, .endef, .dim, .file, .scl, .size, .tag, .type, .val, .stabd, .stabn, and .stabs. The debugging information generated by the three .stab directives can only be read by GDB, not by traditional MIPS debuggers (this enhancement is required to fully support C++ debugging). These directives are primarily used by compilers, not assembly language programmers!

Node:MIPS ISA, Next:, Previous:MIPS Stabs, Up:MIPS-Dependent

Directives to override the ISA level

GNU as supports an additional directive to change the MIPS Instruction Set Architecture level on the fly: .set mipsn. n should be a number from 0 to 5, or 32 or 64. The values 1 to 5, 32, and 64 make the assembler accept instructions for the corresponding ISA level, from that point on in the assembly. .set mipsn affects not only which instructions are permitted, but also how certain macros are expanded. .set mips0 restores the ISA level to its original level: either the level you selected with command line options, or the default for your configuration. You can use this feature to permit specific R4000 instructions while assembling in 32 bit mode. Use this directive with care!

The directive .set mips16 puts the assembler into MIPS 16 mode, in which it will assemble instructions for the MIPS 16 processor. Use .set nomips16 to return to normal 32 bit mode.

Traditional MIPS assemblers do not support this directive.

Node:MIPS autoextend, Next:, Previous:MIPS ISA, Up:MIPS-Dependent

Directives for extending MIPS 16 bit instructions

By default, MIPS 16 instructions are automatically extended to 32 bits when necessary. The directive .set noautoextend will turn this off. When .set noautoextend is in effect, any 32 bit instruction must be explicitly extended with the .e modifier (e.g., li.e $4,1000). The directive .set autoextend may be used to once again automatically extend instructions when necessary.

This directive is only meaningful when in MIPS 16 mode. Traditional MIPS assemblers do not support this directive.

Node:MIPS insn, Next:, Previous:MIPS autoextend, Up:MIPS-Dependent

Directive to mark data as an instruction

The .insn directive tells as that the following data is actually instructions. This makes a difference in MIPS 16 mode: when loading the address of a label which precedes instructions, as automatically adds 1 to the value, so that jumping to the loaded address will do the right thing.

Node:MIPS option stack, Previous:MIPS insn, Up:MIPS-Dependent

Directives to save and restore options

The directives .set push and .set pop may be used to save and restore the current settings for all the options which are controlled by .set. The .set push directive saves the current settings on a stack. The .set pop directive pops the stack and restores the settings.

These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro.

Traditional MIPS assemblers do not support these directives.

Node:PDP-11-Dependent, Next:, Previous:SH-Dependent, Up:Machine Dependencies

PDP-11 Dependent Features

Node:PDP-11-Options, Next:, Up:PDP-11-Dependent

Options

The PDP-11 version of as has a rich set of machine dependent options.

Code Generation Options

-mpic | -mno-pic
Generate position-independent (or position-dependent) code.

The default is to generate position-independent code.

Instruction Set Extention Options

These options enables or disables the use of extensions over the base line instruction set as introduced by the first PDP-11 CPU: the KA11. Most options come in two variants: a -mextension that enables extension, and a -mno-extension that disables extension.

The default is to enable all extensions.

-mall | -mall-extensions
Enable all instruction set extensions.
-mno-extensions
Disable all instruction set extensions.
-mcis | -mno-cis
Enable (or disable) the use of the commersial instruction set, which consists of these instructions: ADDNI, ADDN, ADDPI, ADDP, ASHNI, ASHN, ASHPI, ASHP, CMPCI, CMPC, CMPNI, CMPN, CMPPI, CMPP, CVTLNI, CVTLN, CVTLPI, CVTLP, CVTNLI, CVTNL, CVTNPI, CVTNP, CVTPLI, CVTPL, CVTPNI, CVTPN, DIVPI, DIVP, L2DR, L3DR, LOCCI, LOCC, MATCI, MATC, MOVCI, MOVC, MOVRCI, MOVRC, MOVTCI, MOVTC, MULPI, MULP, SCANCI, SCANC, SKPCI, SKPC, SPANCI, SPANC, SUBNI, SUBN, SUBPI, and SUBP.
-mcsm | -mno-csm
Enable (or disable) the use of the CSM instruction.
-meis | -mno-eis
Enable (or disable) the use of the extended instruction set, which consists of these instructions: ASHC, ASH, DIV, MARK, MUL, RTT, SOB SXT, and XOR.
-mfis | -mkev11
-mno-fis | -mno-kev11
Enable (or diasble) the use of the KEV11 floating-point instructions: FADD, FDIV, FMUL, and FSUB.
-mfpp | -mfpu | -mfp-11
-mno-fpp | -mno-fpu | -mno-fp-11
Enable (or disable) the use of FP-11 floating-point instructions: ABSF, ADDF, CFCC, CLRF, CMPF, DIVF, LDCFF, LDCIF, LDEXP, LDF, LDFPS, MODF, MULF, NEGF, SETD, SETF, SETI, SETL, STCFF, STCFI, STEXP, STF, STFPS, STST, SUBF, and TSTF.
-mlimited-eis | -mno-limited-eis
Enable (or disable) the use of the limited extended instruction set: MARK, RTT, SOB, SXT, and XOR.

The -mno-limited-eis options also implies -mno-eis.

-mmfpt | -mno-mfpt
Enable (or disable) the use of the MFPT instruction.
-mmultiproc | -mno-multiproc
Enable (or disable) the use of multiprocessor instructions: TSTSET and WRTLCK.
-mmxps | -mno-mxps
Enable (or disable) the use of the MFPS and MTPS instructions.
-mspl | -mno-spl
Enable (or disable) the use of the SPL instruction.

Enable (or disable) the use of the microcode instructions: LDUB, MED, and XFC.

CPU Model Options

These options enable the instruction set extensions supported by a particular CPU, and disables all other extensions.

-mka11
KA11 CPU. Base line instruction set only.
-mkb11
KB11 CPU. Enable extended instruction set and SPL.
-mkd11a
KD11-A CPU. Enable limited extended instruction set.
-mkd11b
KD11-B CPU. Base line instruction set only.
-mkd11d
KD11-D CPU. Base line instruction set only.
-mkd11e
KD11-E CPU. Enable extended instruction set, MFPS, and MTPS.
-mkd11f | -mkd11h | -mkd11q
KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended instruction set, MFPS, and MTPS.
-mkd11k
KD11-K CPU. Enable extended instruction set, LDUB, MED, MFPS, MFPT, MTPS, and XFC.
-mkd11z
KD11-Z CPU. Enable extended instruction set, CSM, MFPS, MFPT, MTPS, and SPL.
-mf11
F11 CPU. Enable extended instruction set, MFPS, MFPT, and MTPS.
-mj11
J11 CPU. Enable extended instruction set, CSM, MFPS, MFPT, MTPS, SPL, TSTSET, and WRTLCK.
-mt11
T11 CPU. Enable limited extended instruction set, MFPS, and MTPS.

Machine Model Options

These options enable the instruction set extensions supported by a particular machine model, and disables all other extensions.

-m11/03
Same as -mkd11f.
-m11/04
Same as -mkd11d.
-m11/05 | -m11/10
Same as -mkd11b.
-m11/15 | -m11/20
Same as -mka11.
-m11/21
Same as -mt11.
-m11/23 | -m11/24
Same as -mf11.
-m11/34
Same as -mkd11e.
-m11/34a
Ame as -mkd11e -mfpp.
-m11/35 | -m11/40
Same as -mkd11a.
-m11/44
Same as -mkd11z.
-m11/45 | -m11/50 | -m11/55 | -m11/70
Same as -mkb11.
-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94
Same as -mj11.
-m11/60
Same as -mkd11k.

Node:PDP-11-Pseudos, Next:, Previous:PDP-11-Options, Up:PDP-11-Dependent

Assembler Directives

The PDP-11 version of as has a few machine dependent assembler directives.

.bss
Switch to the bss section.
.even
Align the location counter to an even number.

Node:PDP-11-Syntax, Next:, Previous:PDP-11-Pseudos, Up:PDP-11-Dependent

PDP-11 Assembly Language Syntax

as supports both DEC syntax and BSD syntax. The only difference is that in DEC syntax, a # character is used to denote an immediate constants, while in BSD syntax the character for this purpose is $.

eneral-purpose registers are named r0 through r7. Mnemonic alternatives for r6 and r7 are sp and pc, respectively.

Floating-point registers are named ac0 through ac3, or alternatively fr0 through fr3.

Comments are started with a # or a / character, and extend to the end of the line. (FIXME: clash with immediates?)

Node:PDP-11-Mnemonics, Next:, Previous:PDP-11-Syntax, Up:PDP-11-Dependent

Instruction Naming

Some instructions have alternative names.

BCC
BHIS
BCS
BLO
L2DR
L2D
L3DR
L3D
SYS
TRAP

Node:PDP-11-Synthetic, Previous:PDP-11-Mnemonics, Up:PDP-11-Dependent

Synthetic Instructions

The JBR and JCC synthetic instructions are not supported yet.

Node:PJ-Dependent, Next:, Previous:PDP-11-Dependent, Up:Machine Dependencies

picoJava Dependent Features

Node:PJ Options, Up:PJ-Dependent

Options

as has two addiitional command-line options for the picoJava architecture.

-ml
This option selects little endian data output.
-mb
This option selects big endian data output.

Node:SH-Dependent, Next:, Previous:MIPS-Dependent, Up:Machine Dependencies

Hitachi SH Dependent Features

Node:SH Options, Next:, Up:SH-Dependent

Options

as has no additional command-line options for the Hitachi SH family.

Node:SH Syntax, Next:, Previous:SH Options, Up:SH-Dependent

Syntax

Node:SH-Chars, Next:, Up:SH Syntax

Special Characters

! is the line comment character.

You can use ; instead of a newline to separate statements.

Since $ has no special meaning, you may use it in symbol names.

Node:SH-Regs, Next:, Previous:SH-Chars, Up:SH Syntax

Register Names

You can use the predefined symbols r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, and r15 to refer to the SH registers.

The SH also has these control registers:

pr
procedure register (holds return address)
pc
program counter
mach
macl
high and low multiply accumulator registers
sr
status register
gbr
global base register
vbr
vector base register (for interrupt vectors)

Node:SH-Addressing, Previous:SH-Regs, Up:SH Syntax

Addressing Modes

as understands the following addressing modes for the SH. Rn in the following refers to any of the numbered registers, but not the control registers.

Rn
Register direct
@Rn
Register indirect
@-Rn
Register indirect with pre-decrement
@Rn+
Register indirect with post-increment
@(disp, Rn)
Register indirect with displacement
@(R0, Rn)
Register indexed
@(disp, GBR)
GBR offset
@(R0, GBR)
GBR indexed
addr
@(disp, PC)
PC relative address (for branch or for addressing memory). The as implementation allows you to use the simpler form addr anywhere a PC relative address is called for; the alternate form is supported for compatibility with other assemblers.
#imm
Immediate data

Node:SH Floating Point, Next:, Previous:SH Syntax, Up:SH-Dependent

Floating Point

The SH family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.

Node:SH Directives, Next:, Previous:SH Floating Point, Up:SH-Dependent

SH Machine Directives

uaword
ualong
as will issue a warning when a misaligned .word or .long directive is used. You may use .uaword or .ualong to indicate that the value is intentionally misaligned.

Node:SH Opcodes, Previous:SH Directives, Up:SH-Dependent

Opcodes

For detailed information on the SH machine instruction set, see SH-Microcomputer User's Manual (Hitachi Micro Systems, Inc.).

as implements all the standard SH opcodes. No additional pseudo-instructions are needed on this family. Note, however, that because as supports a simpler form of PC-relative addressing, you may simply write (for example) 

mov.l  bar,r0

where other assemblers might require an explicit displacement to bar from the program counter: 

mov.l  @(disp, PC)

Here is a summary of SH opcodes: 

Legend:
Rn        a numbered register
Rm        another numbered register
#imm      immediate data
disp      displacement
disp8     8-bit displacement
disp12    12-bit displacement

add #imm,Rn                    lds.l @Rn+,PR
add Rm,Rn                      mac.w @Rm+,@Rn+
addc Rm,Rn                     mov #imm,Rn
addv Rm,Rn                     mov Rm,Rn
and #imm,R0                    mov.b Rm,@(R0,Rn)
and Rm,Rn                      mov.b Rm,@-Rn
and.b #imm,@(R0,GBR)           mov.b Rm,@Rn
bf disp8                       mov.b @(disp,Rm),R0
bra disp12                     mov.b @(disp,GBR),R0
bsr disp12                     mov.b @(R0,Rm),Rn
bt disp8                       mov.b @Rm+,Rn
clrmac                         mov.b @Rm,Rn
clrt                           mov.b R0,@(disp,Rm)
cmp/eq #imm,R0                 mov.b R0,@(disp,GBR)
cmp/eq Rm,Rn                   mov.l Rm,@(disp,Rn)
cmp/ge Rm,Rn                   mov.l Rm,@(R0,Rn)
cmp/gt Rm,Rn                   mov.l Rm,@-Rn
cmp/hi Rm,Rn                   mov.l Rm,@Rn
cmp/hs Rm,Rn                   mov.l @(disp,Rn),Rm
cmp/pl Rn                      mov.l @(disp,GBR),R0
cmp/pz Rn                      mov.l @(disp,PC),Rn
cmp/str Rm,Rn                  mov.l @(R0,Rm),Rn
div0s Rm,Rn                    mov.l @Rm+,Rn
div0u                          mov.l @Rm,Rn
div1 Rm,Rn                     mov.l R0,@(disp,GBR)
exts.b Rm,Rn                   mov.w Rm,@(R0,Rn)
exts.w Rm,Rn                   mov.w Rm,@-Rn
extu.b Rm,Rn                   mov.w Rm,@Rn
extu.w Rm,Rn                   mov.w @(disp,Rm),R0
jmp @Rn                        mov.w @(disp,GBR),R0
jsr @Rn                        mov.w @(disp,PC),Rn
ldc Rn,GBR                     mov.w @(R0,Rm),Rn
ldc Rn,SR                      mov.w @Rm+,Rn
ldc Rn,VBR                     mov.w @Rm,Rn
ldc.l @Rn+,GBR                 mov.w R0,@(disp,Rm)
ldc.l @Rn+,SR                  mov.w R0,@(disp,GBR)
ldc.l @Rn+,VBR                 mova @(disp,PC),R0
lds Rn,MACH                    movt Rn
lds Rn,MACL                    muls Rm,Rn
lds Rn,PR                      mulu Rm,Rn
lds.l @Rn+,MACH                neg Rm,Rn
lds.l @Rn+,MACL                negc Rm,Rn

nop                            stc VBR,Rn
not Rm,Rn                      stc.l GBR,@-Rn
or #imm,R0                     stc.l SR,@-Rn
or Rm,Rn                       stc.l VBR,@-Rn
or.b #imm,@(R0,GBR)            sts MACH,Rn
rotcl Rn                       sts MACL,Rn
rotcr Rn                       sts PR,Rn
rotl Rn                        sts.l MACH,@-Rn
rotr Rn                        sts.l MACL,@-Rn
rte                            sts.l PR,@-Rn
rts                            sub Rm,Rn
sett                           subc Rm,Rn
shal Rn                        subv Rm,Rn
shar Rn                        swap.b Rm,Rn
shll Rn                        swap.w Rm,Rn
shll16 Rn                      tas.b @Rn
shll2 Rn                       trapa #imm
shll8 Rn                       tst #imm,R0
shlr Rn                        tst Rm,Rn
shlr16 Rn                      tst.b #imm,@(R0,GBR)
shlr2 Rn                       xor #imm,R0
shlr8 Rn                       xor Rm,Rn
sleep                          xor.b #imm,@(R0,GBR)
stc GBR,Rn                     xtrct Rm,Rn
stc SR,Rn

Node:Sparc-Dependent, Next:, Previous:PJ-Dependent, Up:Machine Dependencies

SPARC Dependent Features

Node:Sparc-Opts, Next:, Up:Sparc-Dependent

Options

The SPARC chip family includes several successive levels, using the same core instruction set, but including a few additional instructions at each level. There are exceptions to this however. For details on what instructions each variant supports, please see the chip's architecture reference manual.

By default, as assumes the core instruction set (SPARC v6), but "bumps" the architecture level as needed: it switches to successively higher architectures as it encounters instructions that only exist in the higher levels.

If not configured for SPARC v9 (sparc64-*-*) GAS will not bump passed sparclite by default, an option must be passed to enable the v9 instructions.

GAS treats sparclite as being compatible with v8, unless an architecture is explicitly requested. SPARC v9 is always incompatible with sparclite.

-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite
-Av8plus | -Av8plusa | -Av9 | -Av9a
Use one of the -A options to select one of the SPARC architectures explicitly. If you select an architecture explicitly, as reports a fatal error if it encounters an instruction or feature requiring an incompatible or higher level.

-Av8plus and -Av8plusa select a 32 bit environment.

-Av9 and -Av9a select a 64 bit environment and are not available unless GAS is explicitly configured with 64 bit environment support.

-Av8plusa and -Av9a enable the SPARC V9 instruction set with UltraSPARC extensions.

-xarch=v8plus | -xarch=v8plusa
For compatibility with the Solaris v9 assembler. These options are equivalent to -Av8plus and -Av8plusa, respectively.
-bump
Warn whenever it is necessary to switch to another level. If an architecture level is explicitly requested, GAS will not issue warnings until that level is reached, and will then bump the level as required (except between incompatible levels).
-32 | -64
Select the word size, either 32 bits or 64 bits. These options are only available with the ELF object file format, and require that the necessary BFD support has been included.

Node:Sparc-Aligned-Data, Next:, Previous:Sparc-Opts, Up:Sparc-Dependent

Enforcing aligned data

SPARC GAS normally permits data to be misaligned. For example, it permits the .long pseudo-op to be used on a byte boundary. However, the native SunOS and Solaris assemblers issue an error when they see misaligned data.

You can use the --enforce-aligned-data option to make SPARC GAS also issue an error about misaligned data, just as the SunOS and Solaris assemblers do.

The --enforce-aligned-data option is not the default because gcc issues misaligned data pseudo-ops when it initializes certain packed data structures (structures defined using the packed attribute). You may have to assemble with GAS in order to initialize packed data structures in your own code.

Node:Sparc-Float, Next:, Previous:Sparc-Aligned-Data, Up:Sparc-Dependent

Floating Point

The Sparc uses IEEE floating-point numbers.

Node:Sparc-Directives, Previous:Sparc-Float, Up:Sparc-Dependent

Sparc Machine Directives

The Sparc version of as supports the following additional machine directives:

.align
This must be followed by the desired alignment in bytes.
.common
This must be followed by a symbol name, a positive number, and "bss". This behaves somewhat like .comm, but the syntax is different.
.half
This is functionally identical to .short.
.nword
On the Sparc, the .nword directive produces native word sized value, ie. if assembling with -32 it is equivalent to .word, if assembling with -64 it is equivalent to .xword.
.proc
This directive is ignored. Any text following it on the same line is also ignored.
.register
This directive declares use of a global application or system register. It must be followed by a register name %g2, %g3, %g6 or %g7, comma and the symbol name for that register. If symbol name is #scratch, it is a scratch register, if it is #ignore, it just surpresses any errors about using undeclared global register, but does not emit any information about it into the object file. This can be useful e.g. if you save the register before use and restore it after.
.reserve
This must be followed by a symbol name, a positive number, and "bss". This behaves somewhat like .lcomm, but the syntax is different.
.seg
This must be followed by "text", "data", or "data1". It behaves like .text, .data, or .data 1.
.skip
This is functionally identical to the .space directive.
.word
On the Sparc, the .word directive produces 32 bit values, instead of the 16 bit values it produces on many other machines.
.xword
On the Sparc V9 processor, the .xword directive produces 64 bit values.

Node:Z8000-Dependent, Next:, Previous:V850-Dependent, Up:Machine Dependencies

Z8000 Dependent Features

The Z8000 as supports both members of the Z8000 family: the unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with 24 bit addresses.

When the assembler is in unsegmented mode (specified with the unsegm directive), an address takes up one word (16 bit) sized register. When the assembler is in segmented mode (specified with the segm directive), a 24-bit address takes up a long (32 bit) register. See Assembler Directives for the Z8000, for a list of other Z8000 specific assembler directives.

Node:Z8000 Options, Next:, Up:Z8000-Dependent

Options

as has no additional command-line options for the Zilog Z8000 family.

Node:Z8000 Syntax, Next:, Previous:Z8000 Options, Up:Z8000-Dependent

Syntax

Node:Z8000-Chars, Next:, Up:Z8000 Syntax

Special Characters

! is the line comment character.

You can use ; instead of a newline to separate statements.

Node:Z8000-Regs, Next:, Previous:Z8000-Chars, Up:Z8000 Syntax

Register Names

The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer to different sized groups of registers by register number, with the prefix r for 16 bit registers, rr for 32 bit registers and rq for 64 bit registers. You can also refer to the contents of the first eight (of the sixteen 16 bit registers) by bytes. They are named rnh and rnl. 


byte registers

r0l r0h r1h r1l r2h r2l r3h r3l
r4h r4l r5h r5l r6h r6l r7h r7l


word registers

r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15


long word registers

rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14


quad word registers

rq0 rq4 rq8 rq12

Node:Z8000-Addressing, Previous:Z8000-Regs, Up:Z8000 Syntax

Addressing Modes

as understands the following addressing modes for the Z8000:
rn
Register direct
@rn
Indirect register
addr
Direct: the 16 bit or 24 bit address (depending on whether the assembler is in segmented or unsegmented mode) of the operand is in the instruction.
address(rn)
Indexed: the 16 or 24 bit address is added to the 16 bit register to produce the final address in memory of the operand.
rn(#imm)
Base Address: the 16 or 24 bit register is added to the 16 bit sign extended immediate displacement to produce the final address in memory of the operand.
rn(rm)
Base Index: the 16 or 24 bit register rn is added to the sign extended 16 bit index register rm to produce the final address in memory of the operand.
#xx
Immediate data xx.

Node:Z8000 Directives, Next:, Previous:Z8000 Syntax, Up:Z8000-Dependent

Assembler Directives for the Z8000

The Z8000 port of as includes these additional assembler directives, for compatibility with other Z8000 assemblers. As shown, these do not begin with . (unlike the ordinary as directives).

segm
Generates code for the segmented Z8001.
unsegm
Generates code for the unsegmented Z8002.
name
Synonym for .file
global
Synonym for .global
wval
Synonym for .word
lval
Synonym for .long
bval
Synonym for .byte
sval
Assemble a string. sval expects one string literal, delimited by single quotes. It assembles each byte of the string into consecutive addresses. You can use the escape sequence %xx (where xx represents a two-digit hexadecimal number) to represent the character whose ASCII value is xx. Use this feature to describe single quote and other characters that may not appear in string literals as themselves. For example, the C statement char *a = "he said \"it's 50% off\""; is represented in Z8000 assembly language (shown with the assembler output in hex at the left) as 
68652073    sval    'he said %22it%27s 50%25 off%22%00'
61696420
22697427
73203530
25206F66
662200

rsect
synonym for .section
block
synonym for .space
even
special case of .align; aligns output to even byte boundary.

Node:Z8000 Opcodes, Previous:Z8000 Directives, Up:Z8000-Dependent

Opcodes

For detailed information on the Z8000 machine instruction set, see Z8000 Technical Manual.

The following table summarizes the opcodes and their arguments: 

            rs   16 bit source register
            rd   16 bit destination register
            rbs   8 bit source register
            rbd   8 bit destination register
            rrs   32 bit source register
            rrd   32 bit destination register
            rqs   64 bit source register
            rqd   64 bit destination register
            addr 16/24 bit address
            imm  immediate data

adc rd,rs               clrb addr               cpsir @rd,@rs,rr,cc
adcb rbd,rbs            clrb addr(rd)           cpsirb @rd,@rs,rr,cc
add rd,@rs              clrb rbd                dab rbd
add rd,addr             com @rd                 dbjnz rbd,disp7
add rd,addr(rs)         com addr                dec @rd,imm4m1
add rd,imm16            com addr(rd)            dec addr(rd),imm4m1
add rd,rs               com rd                  dec addr,imm4m1
addb rbd,@rs            comb @rd                dec rd,imm4m1
addb rbd,addr           comb addr               decb @rd,imm4m1
addb rbd,addr(rs)       comb addr(rd)           decb addr(rd),imm4m1
addb rbd,imm8           comb rbd                decb addr,imm4m1
addb rbd,rbs            comflg flags            decb rbd,imm4m1
addl rrd,@rs            cp @rd,imm16            di i2
addl rrd,addr           cp addr(rd),imm16       div rrd,@rs
addl rrd,addr(rs)       cp addr,imm16           div rrd,addr
addl rrd,imm32          cp rd,@rs               div rrd,addr(rs)
addl rrd,rrs            cp rd,addr              div rrd,imm16
and rd,@rs              cp rd,addr(rs)          div rrd,rs
and rd,addr             cp rd,imm16             divl rqd,@rs
and rd,addr(rs)         cp rd,rs                divl rqd,addr
and rd,imm16            cpb @rd,imm8            divl rqd,addr(rs)
and rd,rs               cpb addr(rd),imm8       divl rqd,imm32
andb rbd,@rs            cpb addr,imm8           divl rqd,rrs
andb rbd,addr           cpb rbd,@rs             djnz rd,disp7
andb rbd,addr(rs)       cpb rbd,addr            ei i2
andb rbd,imm8           cpb rbd,addr(rs)        ex rd,@rs
andb rbd,rbs            cpb rbd,imm8            ex rd,addr
bit @rd,imm4            cpb rbd,rbs             ex rd,addr(rs)
bit addr(rd),imm4       cpd rd,@rs,rr,cc        ex rd,rs
bit addr,imm4           cpdb rbd,@rs,rr,cc      exb rbd,@rs
bit rd,imm4             cpdr rd,@rs,rr,cc       exb rbd,addr
bit rd,rs               cpdrb rbd,@rs,rr,cc     exb rbd,addr(rs)
bitb @rd,imm4           cpi rd,@rs,rr,cc        exb rbd,rbs
bitb addr(rd),imm4      cpib rbd,@rs,rr,cc      ext0e imm8
bitb addr,imm4          cpir rd,@rs,rr,cc       ext0f imm8
bitb rbd,imm4           cpirb rbd,@rs,rr,cc     ext8e imm8
bitb rbd,rs             cpl rrd,@rs             ext8f imm8
bpt                     cpl rrd,addr            exts rrd
call @rd                cpl rrd,addr(rs)        extsb rd
call addr               cpl rrd,imm32           extsl rqd
call addr(rd)           cpl rrd,rrs             halt
calr disp12             cpsd @rd,@rs,rr,cc      in rd,@rs
clr @rd                 cpsdb @rd,@rs,rr,cc     in rd,imm16
clr addr                cpsdr @rd,@rs,rr,cc     inb rbd,@rs
clr addr(rd)            cpsdrb @rd,@rs,rr,cc    inb rbd,imm16
clr rd                  cpsi @rd,@rs,rr,cc      inc @rd,imm4m1
clrb @rd                cpsib @rd,@rs,rr,cc     inc addr(rd),imm4m1
inc addr,imm4m1         ldb rbd,rs(rx)          mult rrd,addr(rs)
inc rd,imm4m1           ldb rd(imm16),rbs       mult rrd,imm16
incb @rd,imm4m1         ldb rd(rx),rbs          mult rrd,rs
incb addr(rd),imm4m1    ldctl ctrl,rs           multl rqd,@rs
incb addr,imm4m1        ldctl rd,ctrl           multl rqd,addr
incb rbd,imm4m1         ldd @rs,@rd,rr          multl rqd,addr(rs)
ind @rd,@rs,ra          lddb @rs,@rd,rr         multl rqd,imm32
indb @rd,@rs,rba        lddr @rs,@rd,rr         multl rqd,rrs
inib @rd,@rs,ra         lddrb @rs,@rd,rr        neg @rd
inibr @rd,@rs,ra        ldi @rd,@rs,rr          neg addr
iret                    ldib @rd,@rs,rr         neg addr(rd)
jp cc,@rd               ldir @rd,@rs,rr         neg rd
jp cc,addr              ldirb @rd,@rs,rr        negb @rd
jp cc,addr(rd)          ldk rd,imm4             negb addr
jr cc,disp8             ldl @rd,rrs             negb addr(rd)
ld @rd,imm16            ldl addr(rd),rrs        negb rbd
ld @rd,rs               ldl addr,rrs            nop
ld addr(rd),imm16       ldl rd(imm16),rrs       or rd,@rs
ld addr(rd),rs          ldl rd(rx),rrs          or rd,addr
ld addr,imm16           ldl rrd,@rs             or rd,addr(rs)
ld addr,rs              ldl rrd,addr            or rd,imm16
ld rd(imm16),rs         ldl rrd,addr(rs)        or rd,rs
ld rd(rx),rs            ldl rrd,imm32           orb rbd,@rs
ld rd,@rs               ldl rrd,rrs             orb rbd,addr
ld rd,addr              ldl rrd,rs(imm16)       orb rbd,addr(rs)
ld rd,addr(rs)          ldl rrd,rs(rx)          orb rbd,imm8
ld rd,imm16             ldm @rd,rs,n            orb rbd,rbs
ld rd,rs                ldm addr(rd),rs,n       out @rd,rs
ld rd,rs(imm16)         ldm addr,rs,n           out imm16,rs
ld rd,rs(rx)            ldm rd,@rs,n            outb @rd,rbs
lda rd,addr             ldm rd,addr(rs),n       outb imm16,rbs
lda rd,addr(rs)         ldm rd,addr,n           outd @rd,@rs,ra
lda rd,rs(imm16)        ldps @rs                outdb @rd,@rs,rba
lda rd,rs(rx)           ldps addr               outib @rd,@rs,ra
ldar rd,disp16          ldps addr(rs)           outibr @rd,@rs,ra
ldb @rd,imm8            ldr disp16,rs           pop @rd,@rs
ldb @rd,rbs             ldr rd,disp16           pop addr(rd),@rs
ldb addr(rd),imm8       ldrb disp16,rbs         pop addr,@rs
ldb addr(rd),rbs        ldrb rbd,disp16         pop rd,@rs
ldb addr,imm8           ldrl disp16,rrs         popl @rd,@rs
ldb addr,rbs            ldrl rrd,disp16         popl addr(rd),@rs
ldb rbd,@rs             mbit                    popl addr,@rs
ldb rbd,addr            mreq rd                 popl rrd,@rs
ldb rbd,addr(rs)        mres                    push @rd,@rs
ldb rbd,imm8            mset                    push @rd,addr
ldb rbd,rbs             mult rrd,@rs            push @rd,addr(rs)
ldb rbd,rs(imm16)       mult rrd,addr           push @rd,imm16
push @rd,rs             set addr,imm4           subl rrd,imm32
pushl @rd,@rs           set rd,imm4             subl rrd,rrs
pushl @rd,addr          set rd,rs               tcc cc,rd
pushl @rd,addr(rs)      setb @rd,imm4           tccb cc,rbd
pushl @rd,rrs           setb addr(rd),imm4      test @rd
res @rd,imm4            setb addr,imm4          test addr
res addr(rd),imm4       setb rbd,imm4           test addr(rd)
res addr,imm4           setb rbd,rs             test rd
res rd,imm4             setflg imm4             testb @rd
res rd,rs               sinb rbd,imm16          testb addr
resb @rd,imm4           sinb rd,imm16           testb addr(rd)
resb addr(rd),imm4      sind @rd,@rs,ra         testb rbd
resb addr,imm4          sindb @rd,@rs,rba       testl @rd
resb rbd,imm4           sinib @rd,@rs,ra        testl addr
resb rbd,rs             sinibr @rd,@rs,ra       testl addr(rd)
resflg imm4             sla rd,imm8             testl rrd
ret cc                  slab rbd,imm8           trdb @rd,@rs,rba
rl rd,imm1or2           slal rrd,imm8           trdrb @rd,@rs,rba
rlb rbd,imm1or2         sll rd,imm8             trib @rd,@rs,rbr
rlc rd,imm1or2          sllb rbd,imm8           trirb @rd,@rs,rbr
rlcb rbd,imm1or2        slll rrd,imm8           trtdrb @ra,@rb,rbr
rldb rbb,rba            sout imm16,rs           trtib @ra,@rb,rr
rr rd,imm1or2           soutb imm16,rbs         trtirb @ra,@rb,rbr
rrb rbd,imm1or2         soutd @rd,@rs,ra        trtrb @ra,@rb,rbr
rrc rd,imm1or2          soutdb @rd,@rs,rba      tset @rd
rrcb rbd,imm1or2        soutib @rd,@rs,ra       tset addr
rrdb rbb,rba            soutibr @rd,@rs,ra      tset addr(rd)
rsvd36                  sra rd,imm8             tset rd
rsvd38                  srab rbd,imm8           tsetb @rd
rsvd78                  sral rrd,imm8           tsetb addr
rsvd7e                  srl rd,imm8             tsetb addr(rd)
rsvd9d                  srlb rbd,imm8           tsetb rbd
rsvd9f                  srll rrd,imm8           xor rd,@rs
rsvdb9                  sub rd,@rs              xor rd,addr
rsvdbf                  sub rd,addr             xor rd,addr(rs)
sbc rd,rs               sub rd,addr(rs)         xor rd,imm16
sbcb rbd,rbs            sub rd,imm16            xor rd,rs
sc imm8                 sub rd,rs               xorb rbd,@rs
sda rd,rs               subb rbd,@rs            xorb rbd,addr
sdab rbd,rs             subb rbd,addr           xorb rbd,addr(rs)
sdal rrd,rs             subb rbd,addr(rs)       xorb rbd,imm8
sdl rd,rs               subb rbd,imm8           xorb rbd,rbs
sdlb rbd,rs             subb rbd,rbs            xorb rbd,rbs
sdll rrd,rs             subl rrd,@rs
set @rd,imm4            subl rrd,addr
set addr(rd),imm4       subl rrd,addr(rs)

Node:Vax-Dependent, Previous:Z8000-Dependent, Up:Machine Dependencies

VAX Dependent Features

Node:VAX-Opts, Next:, Up:Vax-Dependent

VAX Command-Line Options

The Vax version of as accepts any of the following options, gives a warning message that the option was ignored and proceeds. These options are for compatibility with scripts designed for other people's assemblers.

-D (Debug)
-S (Symbol Table)
-T (Token Trace)
These are obsolete options used to debug old assemblers.
-d (Displacement size for JUMPs)
This option expects a number following the -d. Like options that expect filenames, the number may immediately follow the -d (old standard) or constitute the whole of the command line argument that follows -d (GNU standard).
-V (Virtualize Interpass Temporary File)
Some other assemblers use a temporary file. This option commanded them to keep the information in active memory rather than in a disk file. as always does this, so this option is redundant.
-J (JUMPify Longer Branches)
Many 32-bit computers permit a variety of branch instructions to do the same job. Some of these instructions are short (and fast) but have a limited range; others are long (and slow) but can branch anywhere in virtual memory. Often there are 3 flavors of branch: short, medium and long. Some other assemblers would emit short and medium branches, unless told by this option to emit short and long branches.
-t (Temporary File Directory)
Some other assemblers may use a temporary file, and this option takes a filename being the directory to site the temporary file. Since as does not use a temporary disk file, this option makes no difference. -t needs exactly one filename.

The Vax version of the assembler accepts additional options when compiled for VMS:

-h n
External symbol or section (used for global variables) names are not case sensitive on VAX/VMS and always mapped to upper case. This is contrary to the C language definition which explicitly distinguishes upper and lower case. To implement a standard conforming C compiler, names must be changed (mapped) to preserve the case information. The default mapping is to convert all lower case characters to uppercase and adding an underscore followed by a 6 digit hex value, representing a 24 digit binary value. The one digits in the binary value represent which characters are uppercase in the original symbol name.

The -h n option determines how we map names. This takes several values. No -h switch at all allows case hacking as described above. A value of zero (-h0) implies names should be upper case, and inhibits the case hack. A value of 2 (-h2) implies names should be all lower case, with no case hack. A value of 3 (-h3) implies that case should be preserved. The value 1 is unused. The -H option directs as to display every mapped symbol during assembly.

Symbols whose names include a dollar sign $ are exceptions to the general name mapping. These symbols are normally only used to reference VMS library names. Such symbols are always mapped to upper case.

-+
The -+ option causes as to truncate any symbol name larger than 31 characters. The -+ option also prevents some code following the _main symbol normally added to make the object file compatible with Vax-11 "C".
-1
This option is ignored for backward compatibility with as version 1.x.
-H
The -H option causes as to print every symbol which was changed by case mapping.

Node:VAX-float, Next:, Previous:VAX-Opts, Up:Vax-Dependent

VAX Floating Point

Conversion of flonums to floating point is correct, and compatible with previous assemblers. Rounding is towards zero if the remainder is exactly half the least significant bit.

D, F, G and H floating point formats are understood.

Immediate floating literals (e.g. S`$6.9) are rendered correctly. Again, rounding is towards zero in the boundary case.

The .float directive produces f format numbers. The .double directive produces d format numbers.

Node:VAX-directives, Next:, Previous:VAX-float, Up:Vax-Dependent

Vax Machine Directives

The Vax version of the assembler supports four directives for generating Vax floating point constants. They are described in the table below.

.dfloat
This expects zero or more flonums, separated by commas, and assembles Vax d format 64-bit floating point constants.
.ffloat
This expects zero or more flonums, separated by commas, and assembles Vax f format 32-bit floating point constants.
.gfloat
This expects zero or more flonums, separated by commas, and assembles Vax g format 64-bit floating point constants.
.hfloat
This expects zero or more flonums, separated by commas, and assembles Vax h format 128-bit floating point constants.

Node:VAX-opcodes, Next:, Previous:VAX-directives, Up:Vax-Dependent

VAX Opcodes

All DEC mnemonics are supported. Beware that case... instructions have exactly 3 operands. The dispatch table that follows the case... instruction should be made with .word statements. This is compatible with all unix assemblers we know of.

Node:VAX-branch, Next:, Previous:VAX-opcodes, Up:Vax-Dependent

VAX Branch Improvement

Certain pseudo opcodes are permitted. They are for branch instructions. They expand to the shortest branch instruction that reaches the target. Generally these mnemonics are made by substituting j for b at the start of a DEC mnemonic. This feature is included both for compatibility and to help compilers. If you do not need this feature, avoid these opcodes. Here are the mnemonics, and the code they can expand into.

jbsb
Jsb is already an instruction mnemonic, so we chose jbsb.
(byte displacement)
bsbb ...
(word displacement)
bsbw ...
(long displacement)
jsb ...

jbr
jr
Unconditional branch.
(byte displacement)
brb ...
(word displacement)
brw ...
(long displacement)
jmp ...

jCOND
COND may be any one of the conditional branches neq, nequ, eql, eqlu, gtr, geq, lss, gtru, lequ, vc, vs, gequ, cc, lssu, cs. COND may also be one of the bit tests bs, bc, bss, bcs, bsc, bcc, bssi, bcci, lbs, lbc. NOTCOND is the opposite condition to COND.
(byte displacement)
bCOND ...
(word displacement)
bNOTCOND foo ; brw ... ; foo:
(long displacement)
bNOTCOND foo ; jmp ... ; foo:

jacbX
X may be one of b d f g h l w.
(word displacement)
OPCODE ...
(long displacement) 
OPCODE ..., foo ;
brb bar ;
foo: jmp ... ;
bar:

jaobYYY
YYY may be one of lss leq.
jsobZZZ
ZZZ may be one of geq gtr.
(byte displacement)
OPCODE ...
(word displacement) 
OPCODE ..., foo ;
brb bar ;
foo: brw destination ;
bar:

(long displacement) 
OPCODE ..., foo ;
brb bar ;
foo: jmp destination ;
bar:

aobleq
aoblss
sobgeq
sobgtr
(byte displacement)
OPCODE ...
(word displacement) 
OPCODE ..., foo ;
brb bar ;
foo: brw destination ;
bar:

(long displacement) 
OPCODE ..., foo ;
brb bar ;
foo: jmp destination ;
bar:

Node:VAX-operands, Next:, Previous:VAX-branch, Up:Vax-Dependent

VAX Operands

The immediate character is $ for Unix compatibility, not # as DEC writes it.

The indirect character is * for Unix compatibility, not @ as DEC writes it.

The displacement sizing character is ` (an accent grave) for Unix compatibility, not ^ as DEC writes it. The letter preceding ` may have either case. G is not understood, but all other letters (b i l s w) are understood.

Register names understood are r0 r1 r2 ... r15 ap fp sp pc. Upper and lower case letters are equivalent.

For instance 

tstb *w`$4(r5)

Any expression is permitted in an operand. Operands are comma separated.

Node:VAX-no, Previous:VAX-operands, Up:Vax-Dependent

Not Supported on VAX

Vax bit fields can not be assembled with as. Someone can add the required code if they really need it.

Node:V850-Dependent, Next:, Previous:Sparc-Dependent, Up:Machine Dependencies

v850 Dependent Features

Node:V850 Options, Next:, Up:V850-Dependent

Options

as supports the following additional command-line options for the V850 processor family:


-wsigned_overflow
Causes warnings to be produced when signed immediate values overflow the space available for then within their opcodes. By default this option is disabled as it is possible to receive spurious warnings due to using exact bit patterns as immediate constants.
-wunsigned_overflow
Causes warnings to be produced when unsigned immediate values overflow the space available for then within their opcodes. By default this option is disabled as it is possible to receive spurious warnings due to using exact bit patterns as immediate constants.
-mv850
Specifies that the assembled code should be marked as being targeted at the V850 processor. This allows the linker to detect attempts to link such code with code assembled for other processors.
-mv850e
Specifies that the assembled code should be marked as being targeted at the V850E processor. This allows the linker to detect attempts to link such code with code assembled for other processors.
-mv850any
Specifies that the assembled code should be marked as being targeted at the V850 processor but support instructions that are specific to the extended variants of the process. This allows the production of binaries that contain target specific code, but which are also intended to be used in a generic fashion. For example libgcc.a contains generic routines used by the code produced by GCC for all versions of the v850 architecture, together with support routines only used by the V850E architecture.

Node:V850 Syntax, Next:, Previous:V850 Options, Up:V850-Dependent

Syntax

Node:V850-Chars, Next:, Up:V850 Syntax

Special Characters

# is the line comment character.

Node:V850-Regs, Previous:V850-Chars, Up:V850 Syntax

Register Names

as supports the following names for registers:

general register 0
r0, zero
general register 1
r1
general register 2
r2, hp
general register 3
r3, sp
general register 4
r4, gp
general register 5
r5, tp
general register 6
r6
general register 7
r7
general register 8
r8
general register 9
r9
general register 10
r10
general register 11
r11
general register 12
r12
general register 13
r13
general register 14
r14
general register 15
r15
general register 16
r16
general register 17
r17
general register 18
r18
general register 19
r19
general register 20
r20
general register 21
r21
general register 22
r22
general register 23
r23
general register 24
r24
general register 25
r25
general register 26
r26
general register 27
r27
general register 28
r28
general register 29
r29
general register 30
r30, ep
general register 31
r31, lp
system register 0
eipc
system register 1
eipsw
system register 2
fepc
system register 3
fepsw
system register 4
ecr
system register 5
psw
system register 16
ctpc
system register 17
ctpsw
system register 18
dbpc
system register 19
dbpsw
system register 20
ctbp

Node:V850 Floating Point, Next:, Previous:V850 Syntax, Up:V850-Dependent

Floating Point

The V850 family uses IEEE floating-point numbers.

Node:V850 Directives, Next:, Previous:V850 Floating Point, Up:V850-Dependent

V850 Machine Directives

.offset <expression>
Moves the offset into the current section to the specified amount.
.section "name", <type>
This is an extension to the standard .section directive. It sets the current section to be <type> and creates an alias for this section called "name".
.v850
Specifies that the assembled code should be marked as being targeted at the V850 processor. This allows the linker to detect attempts to link such code with code assembled for other processors.
.v850e
Specifies that the assembled code should be marked as being targeted at the V850E processor. This allows the linker to detect attempts to link such code with code assembled for other processors.

Node:V850 Opcodes, Previous:V850 Directives, Up:V850-Dependent

Opcodes

as implements all the standard V850 opcodes.

as also implements the following pseudo ops:


hi0()
Computes the higher 16 bits of the given expression and stores it into the immediate operand field of the given instruction. For example:

mulhi hi0(here - there), r5, r6

computes the difference between the address of labels 'here' and 'there', takes the upper 16 bits of this difference, shifts it down 16 bits and then mutliplies it by the lower 16 bits in register 5, putting the result into register 6.

lo()
Computes the lower 16 bits of the given expression and stores it into the immediate operand field of the given instruction. For example:

addi lo(here - there), r5, r6

computes the difference between the address of labels 'here' and 'there', takes the lower 16 bits of this difference and adds it to register 5, putting the result into register 6.

hi()
Computes the higher 16 bits of the given expression and then adds the value of the most significant bit of the lower 16 bits of the expression and stores the result into the immediate operand field of the given instruction. For example the following code can be used to compute the address of the label 'here' and store it into register 6:

movhi hi(here), r0, r6 movea lo(here), r6, r6

The reason for this special behaviour is that movea performs a sign extention on its immediate operand. So for example if the address of 'here' was 0xFFFFFFFF then without the special behaviour of the hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the movea instruction would takes its immediate operand, 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). With the hi() pseudo op adding in the top bit of the lo() pseudo op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 - the right value.

hilo()
Computes the 32 bit value of the given expression and stores it into the immediate operand field of the given instruction (which must be a mov instruction). For example:

mov hilo(here), r6

computes the absolute address of label 'here' and puts the result into register 6.

sdaoff()
Computes the offset of the named variable from the start of the Small Data Area (whoes address is held in register 4, the GP register) and stores the result as a 16 bit signed value in the immediate operand field of the given instruction. For example:

ld.w sdaoff(_a_variable)[gp],r6

loads the contents of the location pointed to by the label '_a_variable' into register 6, provided that the label is located somewhere within +/- 32K of the address held in the GP register. [Note the linker assumes that the GP register contains a fixed address set to the address of the label called '__gp'. This can either be set up automatically by the linker, or specifically set by using the --defsym __gp=<value> command line option].

tdaoff()
Computes the offset of the named variable from the start of the Tiny Data Area (whoes address is held in register 30, the EP register) and stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate operand field of the given instruction. For example:

sld.w tdaoff(_a_variable)[ep],r6

loads the contents of the location pointed to by the label '_a_variable' into register 6, provided that the label is located somewhere within +256 bytes of the address held in the EP register. [Note the linker assumes that the EP register contains a fixed address set to the address of the label called '__ep'. This can either be set up automatically by the linker, or specifically set by using the --defsym __ep=<value> command line option].

zdaoff()
Computes the offset of the named variable from address 0 and stores the result as a 16 bit signed value in the immediate operand field of the given instruction. For example:

movea zdaoff(_a_variable),zero,r6

puts the address of the label '_a_variable' into register 6, assuming that the label is somewhere within the first 32K of memory. (Strictly speaking it also possible to access the last 32K of memory as well, as the offsets are signed).

ctoff()
Computes the offset of the named variable from the start of the Call Table Area (whoes address is helg in system register 20, the CTBP register) and stores the result a 6 or 16 bit unsigned value in the immediate field of then given instruction or piece of data. For example:

callt ctoff(table_func1)

will put the call the function whoes address is held in the call table at the location labeled 'table_func1'.

For information on the V850 instruction set, see V850 Family 32-/16-Bit single-Chip Microcontroller Architecture Manual from NEC. Ltd.

Node:Reporting Bugs, Next:, Previous:Machine Dependencies, Up:Top

Reporting Bugs

Your bug reports play an essential role in making as reliable.

Reporting a bug may help you by bringing a solution to your problem, or it may not. But in any case the principal function of a bug report is to help the entire community by making the next version of as work better. Bug reports are your contribution to the maintenance of as.

In order for a bug report to serve its purpose, you must include the information that enables us to fix the bug.

Node:Bug Criteria, Next:, Up:Reporting Bugs

Have you found a bug?

If you are not sure whether you have found a bug, here are some guidelines:

Node:Bug Reporting, Previous:Bug Criteria, Up:Reporting Bugs

How to report bugs

A number of companies and individuals offer support for GNU products. If you obtained as from a support organization, we recommend you contact that organization first.

You can find contact information for many support companies and individuals in the file etc/SERVICE in the GNU Emacs distribution.

In any event, we also recommend that you send bug reports for as to bug-binutils@gnu.org.

The fundamental principle of reporting bugs usefully is this: report all the facts. If you are not sure whether to state a fact or leave it out, state it!

Often people omit facts because they think they know what causes the problem and assume that some details do not matter. Thus, you might assume that the name of a symbol you use in an example does not matter. Well, probably it does not, but one cannot be sure. Perhaps the bug is a stray memory reference which happens to fetch from the location where that name is stored in memory; perhaps, if the name were different, the contents of that location would fool the assembler into doing the right thing despite the bug. Play it safe and give a specific, complete example. That is the easiest thing for you to do, and the most helpful.

Keep in mind that the purpose of a bug report is to enable us to fix the bug if it is new to us. Therefore, always write your bug reports on the assumption that the bug has not been reported previously.

Sometimes people give a few sketchy facts and ask, "Does this ring a bell?" Those bug reports are useless, and we urge everyone to refuse to respond to them except to chide the sender to report bugs properly.

To enable us to fix the bug, you should include all these things:

Here are some things that are not necessary:

Node:Acknowledgements, Next:, Previous:Reporting Bugs, Up:Top

Acknowledgements

If you have contributed to as and your name isn't listed here, it is not meant as a slight. We just don't know about it. Send mail to the maintainer, and we'll correct the situation. Currently the maintainer is Ken Raeburn (email address raeburn@cygnus.com).

Dean Elsner wrote the original GNU assembler for the VAX.1

Jay Fenlason maintained GAS for a while, adding support for GDB-specific debug information and the 68k series machines, most of the preprocessing pass, and extensive changes in messages.c, input-file.c, write.c.

K. Richard Pixley maintained GAS for a while, adding various enhancements and many bug fixes, including merging support for several processors, breaking GAS up to handle multiple object file format back ends (including heavy rewrite, testing, an integration of the coff and b.out back ends), adding configuration including heavy testing and verification of cross assemblers and file splits and renaming, converted GAS to strictly ANSI C including full prototypes, added support for m680[34]0 and cpu32, did considerable work on i960 including a COFF port (including considerable amounts of reverse engineering), a SPARC opcode file rewrite, DECstation, rs6000, and hp300hpux host ports, updated "know" assertions and made them work, much other reorganization, cleanup, and lint.

Ken Raeburn wrote the high-level BFD interface code to replace most of the code in format-specific I/O modules.

The original VMS support was contributed by David L. Kashtan. Eric Youngdale has done much work with it since.

The Intel 80386 machine description was written by Eliot Dresselhaus.

Minh Tran-Le at IntelliCorp contributed some AIX 386 support.

The Motorola 88k machine description was contributed by Devon Bowen of Buffalo University and Torbjorn Granlund of the Swedish Institute of Computer Science.

Keith Knowles at the Open Software Foundation wrote the original MIPS back end (tc-mips.c, tc-mips.h), and contributed Rose format support (which hasn't been merged in yet). Ralph Campbell worked with the MIPS code to support a.out format.

Support for the Zilog Z8k and Hitachi H8/300 and H8/500 processors (tc-z8k, tc-h8300, tc-h8500), and IEEE 695 object file format (obj-ieee), was written by Steve Chamberlain of Cygnus Support. Steve also modified the COFF back end to use BFD for some low-level operations, for use with the H8/300 and AMD 29k targets.

John Gilmore built the AMD 29000 support, added .include support, and simplified the configuration of which versions accept which directives. He updated the 68k machine description so that Motorola's opcodes always produced fixed-size instructions (e.g. jsr), while synthetic instructions remained shrinkable (jbsr). John fixed many bugs, including true tested cross-compilation support, and one bug in relaxation that took a week and required the proverbial one-bit fix.

Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax for the 68k, completed support for some COFF targets (68k, i386 SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets, wrote the initial RS/6000 and PowerPC assembler, and made a few other minor patches.

Steve Chamberlain made as able to generate listings.

Hewlett-Packard contributed support for the HP9000/300.

Jeff Law wrote GAS and BFD support for the native HPPA object format (SOM) along with a fairly extensive HPPA testsuite (for both SOM and ELF object formats). This work was supported by both the Center for Software Science at the University of Utah and Cygnus Support.

Support for ELF format files has been worked on by Mark Eichin of Cygnus Support (original, incomplete implementation for SPARC), Pete Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), Michael Meissner of the Open Software Foundation (i386 mainly), and Ken Raeburn of Cygnus Support (sparc, and some initial 64-bit support).

Linas Vepstas added GAS support for the ESA/390 "IBM 370" architecture.

Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote GAS and BFD support for openVMS/Alpha.

Timothy Wall, Michael Hayes, and Greg Smart contributed to the various tic* flavors.

Several engineers at Cygnus Support have also provided many small bug fixes and configuration enhancements.

Many others have contributed large or small bugfixes and enhancements. If you have contributed significant work and are not mentioned on this list, and want to be, let us know. Some of the history has been lost; we are not intentionally leaving anyone out.

Node:GNU Free Documentation License, Next:, Previous:Acknowledgements, Up:Top

GNU Free Documentation License

GNU Free Documentation License

Version 1.1, March 2000

Copyright (C) 2000 Free Software Foundation, Inc. 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA

Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.

0. PREAMBLE

The purpose of this License is to make a manual, textbook, or other written document "free" in the sense of freedom: to assure everyone the effective freedom to copy and redistribute it, with or without modifying it, either commercially or noncommercially. Secondarily, this License preserves for the author and publisher a way to get credit for their work, while not being considered responsible for modifications made by others.

This License is a kind of "copyleft", which means that derivative works of the document must themselves be free in the same sense. It complements the GNU General Public License, which is a copyleft license designed for free software.

We have designed this License in order to use it for manuals for free software, because free software needs free documentation: a free program should come with manuals providing the same freedoms that the software does. But this License is not limited to software manuals; it can be used for any textual work, regardless of subject matter or whether it is published as a printed book. We recommend this License principally for works whose purpose is instruction or reference.

1. APPLICABILITY AND DEFINITIONS

This License applies to any manual or other work that contains a notice placed by the copyright holder saying it can be distributed under the terms of this License. The "Document", below, refers to any such manual or work. Any member of the public is a licensee, and is addressed as "you".

A "Modified Version" of the Document means any work containing the Document or a portion of it, either copied verbatim, or with modifications and/or translated into another language.

A "Secondary Section" is a named appendix or a front-matter section of the Document that deals exclusively with the relationship of the publishers or authors of the Document to the Document's overall subject (or to related matters) and contains nothing that could fall directly within that overall subject. (For example, if the Document is in part a textbook of mathematics, a Secondary Section may not explain any mathematics.) The relationship could be a matter of historical connection with the subject or with related matters, or of legal, commercial, philosophical, ethical or political position regarding them.

The "Invariant Sections" are certain Secondary Sections whose titles are designated, as being those of Invariant Sections, in the notice that says that the Document is released under this License.

The "Cover Texts" are certain short passages of text that are listed, as Front-Cover Texts or Back-Cover Texts, in the notice that says that the Document is released under this License.

A "Transparent" copy of the Document means a machine-readable copy, represented in a format whose specification is available to the general public, whose contents can be viewed and edited directly and straightforwardly with generic text editors or (for images composed of pixels) generic paint programs or (for drawings) some widely available drawing editor, and that is suitable for input to text formatters or for automatic translation to a variety of formats suitable for input to text formatters. A copy made in an otherwise Transparent file format whose markup has been designed to thwart or discourage subsequent modification by readers is not Transparent. A copy that is not "Transparent" is called "Opaque".

Examples of suitable formats for Transparent copies include plain ASCII without markup, Texinfo input format, LaTeX input format, SGML or XML using a publicly available DTD, and standard-conforming simple HTML designed for human modification. Opaque formats include PostScript, PDF, proprietary formats that can be read and edited only by proprietary word processors, SGML or XML for which the DTD and/or processing tools are not generally available, and the machine-generated HTML produced by some word processors for output purposes only.

The "Title Page" means, for a printed book, the title page itself, plus such following pages as are needed to hold, legibly, the material this License requires to appear in the title page. For works in formats which do not have any title page as such, "Title Page" means the text near the most prominent appearance of the work's title, preceding the beginning of the body of the text.

2. VERBATIM COPYING

You may copy and distribute the Document in any medium, either commercially or noncommercially, provided that this License, the copyright notices, and the license notice saying this License applies to the Document are reproduced in all copies, and that you add no other conditions whatsoever to those of this License. You may not use technical measures to obstruct or control the reading or further copying of the copies you make or distribute. However, you may accept compensation in exchange for copies. If you distribute a large enough number of copies you must also follow the conditions in section 3.

You may also lend copies, under the same conditions stated above, and you may publicly display copies.

3. COPYING IN QUANTITY

If you publish printed copies of the Document numbering more than 100, and the Document's license notice requires Cover Texts, you must enclose the copies in covers that carry, clearly and legibly, all these Cover Texts: Front-Cover Texts on the front cover, and Back-Cover Texts on the back cover. Both covers must also clearly and legibly identify you as the publisher of these copies. The front cover must present the full title with all words of the title equally prominent and visible. You may add other material on the covers in addition. Copying with changes limited to the covers, as long as they preserve the title of the Document and satisfy these conditions, can be treated as verbatim copying in other respects.

If the required texts for either cover are too voluminous to fit legibly, you should put the first ones listed (as many as fit reasonably) on the actual cover, and continue the rest onto adjacent pages.

If you publish or distribute Opaque copies of the Document numbering more than 100, you must either include a machine-readable Transparent copy along with each Opaque copy, or state in or with each Opaque copy a publicly-accessible computer-network location containing a complete Transparent copy of the Document, free of added material, which the general network-using public has access to download anonymously at no charge using public-standard network protocols. If you use the latter option, you must take reasonably prudent steps, when you begin distribution of Opaque copies in quantity, to ensure that this Transparent copy will remain thus accessible at the stated location until at least one year after the last time you distribute an Opaque copy (directly or through your agents or retailers) of that edition to the public.

It is requested, but not required, that you contact the authors of the Document well before redistributing any large number of copies, to give them a chance to provide you with an updated version of the Document.

4. MODIFICATIONS

You may copy and distribute a Modified Version of the Document under the conditions of sections 2 and 3 above, provided that you release the Modified Version under precisely this License, with the Modified Version filling the role of the Document, thus licensing distribution and modification of the Modified Version to whoever possesses a copy of it. In addition, you must do these things in the Modified Version:

A. Use in the Title Page (and on the covers, if any) a title distinct from that of the Document, and from those of previous versions (which should, if there were any, be listed in the History section of the Document). You may use the same title as a previous version if the original publisher of that version gives permission. B. List on the Title Page, as authors, one or more persons or entities responsible for authorship of the modifications in the Modified Version, together with at least five of the principal authors of the Document (all of its principal authors, if it has less than five). C. State on the Title page the name of the publisher of the Modified Version, as the publisher. D. Preserve all the copyright notices of the Document. E. Add an appropriate copyright notice for your modifications adjacent to the other copyright notices. F. Include, immediately after the copyright notices, a license notice giving the public permission to use the Modified Version under the terms of this License, in the form shown in the Addendum below. G. Preserve in that license notice the full lists of Invariant Sections and required Cover Texts given in the Document's license notice. H. Include an unaltered copy of this License. I. Preserve the section entitled "History", and its title, and add to it an item stating at least the title, year, new authors, and publisher of the Modified Version as given on the Title Page. If there is no section entitled "History" in the Document, create one stating the title, year, authors, and publisher of the Document as given on its Title Page, then add an item describing the Modified Version as stated in the previous sentence. J. Preserve the network location, if any, given in the Document for public access to a Transparent copy of the Document, and likewise the network locations given in the Document for previous versions it was based on. These may be placed in the "History" section. You may omit a network location for a work that was published at least four years before the Document itself, or if the original publisher of the version it refers to gives permission. K. In any section entitled "Acknowledgements" or "Dedications", preserve the section's title, and preserve in the section all the substance and tone of each of the contributor acknowledgements and/or dedications given therein. L. Preserve all the Invariant Sections of the Document, unaltered in their text and in their titles. Section numbers or the equivalent are not considered part of the section titles. M. Delete any section entitled "Endorsements". Such a section may not be included in the Modified Version. N. Do not retitle any existing section as "Endorsements" or to conflict in title with any Invariant Section.

If the Modified Version includes new front-matter sections or appendices that qualify as Secondary Sections and contain no material copied from the Document, you may at your option designate some or all of these sections as invariant. To do this, add their titles to the list of Invariant Sections in the Modified Version's license notice. These titles must be distinct from any other section titles.

You may add a section entitled "Endorsements", provided it contains nothing but endorsements of your Modified Version by various parties-for example, statements of peer review or that the text has been approved by an organization as the authoritative definition of a standard.

You may add a passage of up to five words as a Front-Cover Text, and a passage of up to 25 words as a Back-Cover Text, to the end of the list of Cover Texts in the Modified Version. Only one passage of Front-Cover Text and one of Back-Cover Text may be added by (or through arrangements made by) any one entity. If the Document already includes a cover text for the same cover, previously added by you or by arrangement made by the same entity you are acting on behalf of, you may not add another; but you may replace the old one, on explicit permission from the previous publisher that added the old one.

The author(s) and publisher(s) of the Document do not by this License give permission to use their names for publicity for or to assert or imply endorsement of any Modified Version.

5. COMBINING DOCUMENTS

You may combine the Document with other documents released under this License, under the terms defined in section 4 above for modified versions, provided that you include in the combination all of the Invariant Sections of all of the original documents, unmodified, and list them all as Invariant Sections of your combined work in its license notice.

The combined work need only contain one copy of this License, and multiple identical Invariant Sections may be replaced with a single copy. If there are multiple Invariant Sections with the same name but different contents, make the title of each such section unique by adding at the end of it, in parentheses, the name of the original author or publisher of that section if known, or else a unique number. Make the same adjustment to the section titles in the list of Invariant Sections in the license notice of the combined work.

In the combination, you must combine any sections entitled "History" in the various original documents, forming one section entitled "History"; likewise combine any sections entitled "Acknowledgements", and any sections entitled "Dedications". You must delete all sections entitled "Endorsements."

6. COLLECTIONS OF DOCUMENTS

You may make a collection consisting of the Document and other documents released under this License, and replace the individual copies of this License in the various documents with a single copy that is included in the collection, provided that you follow the rules of this License for verbatim copying of each of the documents in all other respects.

You may extract a single document from such a collection, and distribute it individually under this License, provided you insert a copy of this License into the extracted document, and follow this License in all other respects regarding verbatim copying of that document.

7. AGGREGATION WITH INDEPENDENT WORKS

A compilation of the Document or its derivatives with other separate and independent documents or works, in or on a volume of a storage or distribution medium, does not as a whole count as a Modified Version of the Document, provided no compilation copyright is claimed for the compilation. Such a compilation is called an "aggregate", and this License does not apply to the other self-contained works thus compiled with the Document, on account of their being thus compiled, if they are not themselves derivative works of the Document.

If the Cover Text requirement of section 3 is applicable to these copies of the Document, then if the Document is less than one quarter of the entire aggregate, the Document's Cover Texts may be placed on covers that surround only the Document within the aggregate. Otherwise they must appear on covers around the whole aggregate.

8. TRANSLATION

Translation is considered a kind of modification, so you may distribute translations of the Document under the terms of section 4. Replacing Invariant Sections with translations requires special permission from their copyright holders, but you may include translations of some or all Invariant Sections in addition to the original versions of these Invariant Sections. You may include a translation of this License provided that you also include the original English version of this License. In case of a disagreement between the translation and the original English version of this License, the original English version will prevail.

9. TERMINATION

You may not copy, modify, sublicense, or distribute the Document except as expressly provided for under this License. Any other attempt to copy, modify, sublicense or distribute the Document is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance.

10. FUTURE REVISIONS OF THIS LICENSE

The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. See http://www.gnu.org/copyleft/.

Each version of the License is given a distinguishing version number. If the Document specifies that a particular numbered version of this License "or any later version" applies to it, you have the option of following the terms and conditions either of that specified version or of any later version that has been published (not as a draft) by the Free Software Foundation. If the Document does not specify a version number of this License, you may choose any version ever published (not as a draft) by the Free Software Foundation.

ADDENDUM: How to use this License for your documents

To use this License in a document you have written, include a copy of the License in the document and put the following copyright and license notices just after the title page: 

    Copyright (c)  YEAR  YOUR NAME.
    Permission is granted to copy, distribute and/or modify this document
    under the terms of the GNU Free Documentation License, Version 1.1
    or any later version published by the Free Software Foundation;
    with the Invariant Sections being LIST THEIR TITLES, with the
    Front-Cover Texts being LIST, and with the Back-Cover Texts being LIST.
    A copy of the license is included in the section entitled "GNU
    Free Documentation License".

If you have no Invariant Sections, write "with no Invariant Sections" instead of saying which ones are invariant. If you have no Front-Cover Texts, write "no Front-Cover Texts" instead of "Front-Cover Texts being LIST"; likewise for Back-Cover Texts.

If your document contains nontrivial examples of program code, we recommend releasing these examples in parallel under your choice of free software license, such as the GNU General Public License, to permit their use in free software.

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Footnotes

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